Re: [PATCH 0/2]: Get perf counters working on D-cache aliasing cpus.

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Fri, 2009-09-18 at 10:22 -0700, David Miller wrote:
> From: Peter Zijlstra <a.p.zijlstra@chello.nl>
> Date: Fri, 18 Sep 2009 14:31:36 +0200
> 
> > Ingo just reminded me that we might want to do splice support for perf
> > stuff. My plan was to have the splice thing allocate a new page, flip
> > with a filled one from the buffer and send the filled one down to the
> > splice consumer.
> > 
> > Now having vmap'ed all that complicates stuff enourmously.
> > 
> > Would it also work if we use order-1 pages on your platform instead of
> > order-0, so that they are properly aligned for the d-cache?
> 
> You still have to make sure the order-1 page is order-1 virtually
> aligned in userspace.  But that would help only sparc64 because
> SHMLBA happens to be 16K (2 * smallest supported PAGE_SIZE).
> 
> So, this won't handle sparc32 where the SHMLBA is 4MB.
> 
> MIPS has the same exact problems and has a large SHMLBA too.

Ah, ok, vmalloc it is then. I'll have to come up with another scheme for
splice() then.

Thanks!