From: Borislav Petkov <bp@amd64.org>
To: <mingo@elte.hu>, <hpa@zytor.com>, <tglx@linutronix.de>
Cc: <andreas.herrmann3@amd.com>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 6/7] x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches
Date: Thu, 21 Jan 2010 17:41:32 +0100 [thread overview]
Message-ID: <1264092093-13739-7-git-send-email-bp@amd64.org> (raw)
In-Reply-To: <1264092093-13739-1-git-send-email-bp@amd64.org>
From: Borislav Petkov <borislav.petkov@amd.com>
The cache_disable_[01] attribute in
/sys/devices/system/cpu/cpu?/cache/index[0-3]/
is enabled on all cache levels although only L3 supports it. Add it only
to the cache level that actually supports it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 35 ++++++++++++++++++++++++--------
1 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index cef4fdd..0ce0e8d 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -810,16 +810,24 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
+#define DEFAULT_SYSFS_CACHE_ATTRS \
+ &type.attr, \
+ &level.attr, \
+ &coherency_line_size.attr, \
+ &physical_line_partition.attr, \
+ &ways_of_associativity.attr, \
+ &number_of_sets.attr, \
+ &size.attr, \
+ &shared_cpu_map.attr, \
+ &shared_cpu_list.attr
+
static struct attribute *default_attrs[] = {
- &type.attr,
- &level.attr,
- &coherency_line_size.attr,
- &physical_line_partition.attr,
- &ways_of_associativity.attr,
- &number_of_sets.attr,
- &size.attr,
- &shared_cpu_map.attr,
- &shared_cpu_list.attr,
+ DEFAULT_SYSFS_CACHE_ATTRS,
+ NULL
+};
+
+static struct attribute *default_l3_attrs[] = {
+ DEFAULT_SYSFS_CACHE_ATTRS,
&cache_disable_0.attr,
&cache_disable_1.attr,
NULL
@@ -912,6 +920,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
unsigned int cpu = sys_dev->id;
unsigned long i, j;
struct _index_kobject *this_object;
+ struct _cpuid4_info *this_leaf;
int retval;
retval = cpuid4_cache_sysfs_init(cpu);
@@ -930,6 +939,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
this_object = INDEX_KOBJECT_PTR(cpu, i);
this_object->cpu = cpu;
this_object->index = i;
+
+ this_leaf = CPUID4_INFO_IDX(cpu, i);
+
+ if (this_leaf->can_disable)
+ ktype_cache.default_attrs = default_l3_attrs;
+ else
+ ktype_cache.default_attrs = default_attrs;
+
retval = kobject_init_and_add(&(this_object->kobj),
&ktype_cache,
per_cpu(ici_cache_kobject, cpu),
--
1.6.6
next prev parent reply other threads:[~2010-01-21 16:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-21 16:41 [PATCH -v2 0/7] x86, cacheinfo, amd: L3 Cache Index Disable fixes Borislav Petkov
2010-01-21 16:41 ` [PATCH 1/7] x86, smp: Convert msr-smp.c to an smp library Borislav Petkov
2010-01-21 18:08 ` H. Peter Anvin
2010-01-21 16:41 ` [PATCH 2/7] x86, smp: Adjust native_wbinvd for smp_call_function-helpers Borislav Petkov
2010-01-21 18:07 ` H. Peter Anvin
2010-01-21 18:36 ` Borislav Petkov
2010-01-21 16:41 ` [PATCH 3/7] x86, smp: Add wbinvd_on_all_cpus helper Borislav Petkov
2010-01-21 16:41 ` [PATCH 4/7] intel-agp: Switch to wbinvd_on_all_cpus Borislav Petkov
2010-01-21 16:41 ` [PATCH 5/7] x86, cacheinfo: Fix disabling of L3 cache indices Borislav Petkov
2010-01-21 16:41 ` Borislav Petkov [this message]
2010-01-21 16:41 ` [PATCH 7/7] x86, cacheinfo: Calculate L3 indexes Borislav Petkov
2010-01-21 17:57 ` [PATCH] x86, cacheinfo: Calculate L3 indices Borislav Petkov
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