[Qemu-devel] [PATCH] ahci: handle writes to generic host control registers

[Qemu-devel] [PATCH] ahci: handle writes to generic host control registers

[Sebastian Herbszt]

Handle writes to Generic Host Control registers.

Signed-off-by: Sebastian Herbszt <herbszt@gmx.de>

diff --git a/hw/ahci.c b/hw/ahci.c
index f8e198c..178f9ea 100644
--- a/hw/ahci.c
+++ b/hw/ahci.c
@@ -425,7 +425,6 @@ static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
 static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
 {
 	AHCIState *s = ptr;
-	uint32_t *p;
 	addr=addr&0xfff;
 
 	/* Only aligned reads are allowed on OHCI */
@@ -435,17 +434,30 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
 		return;
 	}
 
-	if(addr<0x20)
-	{
-		switch(addr)
-		{
-			case HOST_IRQ_STAT:
+	if (addr < 0x20) { /* Generic Host Control */
+		switch(addr) {
+			case HOST_CAP: /* R/WO, RO */
+				/* FIXME handle R/WO */
+				break;
+			case HOST_CTL: /* R/W */
+				if (val & HOST_RESET) {
+					DPRINTF("HBA Reset\n");
+					/* FIXME reset? */
+				} else
+					s->control_regs.ghc = val;
+				break;
+			case HOST_IRQ_STAT: /* R/WC, RO */
 				s->control_regs.irqstatus &= ~val; 
 				ahci_check_irq(s);
 				break;
+			case HOST_PORTS_IMPL: /* R/WO, RO */
+				/* FIXME handle R/WO */
+				break;
+			case HOST_VERSION: /* RO */
+				/* FIXME report write? */
+				break;
 			default:
-				/* genernal host control */
-				p=(uint32_t *)&s->control_regs;
+				DPRINTF("write to unknown register 0x%x\n", (unsigned)addr);
 		}
 	}
 	else if(addr>=0x100 && addr<0x300)