* [PATCH RESEND 0/2] Alchemy: use new irq methods
@ 2011-02-11 8:47 Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 1/2] MIPS: Convert to " Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 2/2] Alchemy: " Manuel Lauss
0 siblings, 2 replies; 3+ messages in thread
From: Manuel Lauss @ 2011-02-11 8:47 UTC (permalink / raw)
To: Linux-MIPS; +Cc: Ralf Baechle, Manuel Lauss
[Resending without the umlaut in Ralf's surname]
These 2 patches change the core MIPS and Alchmey irq code to use the
new .irq_xxx methods.
The first patch is a prerequisite to turn on GENERIC_HARDIRQS_NO_DEPRECATED.
I have tested it with the C0 timer and it seems to run well, however the MIPS-MT
bits I cannot test. Someone with capable hardware please test! Thank you!
The second patch changes the core alchemy and DB1200 board irq functions over
to the new .irq_xxx ones.
Run-tested on the DB1200.
Manuel Lauss (2):
MIPS: Convert to new irq methods.
Alchemy: Convert to new irq methods.
arch/mips/Kconfig | 1 +
arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++-----------------
arch/mips/alchemy/devboards/bcsr.c | 18 ++++----
arch/mips/kernel/irq.c | 12 ++++-
arch/mips/kernel/irq_cpu.c | 42 +++++++++---------
5 files changed, 85 insertions(+), 71 deletions(-)
--
1.7.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH RESEND 1/2] MIPS: Convert to new irq methods.
2011-02-11 8:47 [PATCH RESEND 0/2] Alchemy: use new irq methods Manuel Lauss
@ 2011-02-11 8:47 ` Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 2/2] Alchemy: " Manuel Lauss
1 sibling, 0 replies; 3+ messages in thread
From: Manuel Lauss @ 2011-02-11 8:47 UTC (permalink / raw)
To: Linux-MIPS; +Cc: Ralf Baechle, Manuel Lauss
Convert the core MIPS irq code to use the new .irq_xxx methods.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
Tested on DB1200 with C0 timer. The MIPS-MT bits are untested since
I don't have capable hardware.
arch/mips/kernel/irq.c | 12 ++++++++++--
arch/mips/kernel/irq_cpu.c | 42 +++++++++++++++++++++---------------------
2 files changed, 31 insertions(+), 23 deletions(-)
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 4f93db5..b8112cf 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -89,6 +89,9 @@ int show_interrupts(struct seq_file *p, void *v)
{
int i = *(loff_t *) v, j;
struct irqaction * action;
+ struct irq_desc *desc;
+ struct irq_data *data;
+ struct irq_chip *chip;
unsigned long flags;
if (i == 0) {
@@ -100,9 +103,14 @@ int show_interrupts(struct seq_file *p, void *v)
if (i < NR_IRQS) {
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
- action = irq_desc[i].action;
+ desc = irq_to_desc(i);
+ if (!desc)
+ goto skip;
+ action = desc->action;
if (!action)
goto skip;
+ data = irq_get_irq_data(i);
+ chip = irq_data_get_irq_chip(data);
seq_printf(p, "%3d: ", i);
#ifndef CONFIG_SMP
seq_printf(p, "%10u ", kstat_irqs(i));
@@ -110,7 +118,7 @@ int show_interrupts(struct seq_file *p, void *v)
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif
- seq_printf(p, " %14s", irq_desc[i].chip->name);
+ seq_printf(p, " %14s", chip->name);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe..91a8689 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -37,25 +37,25 @@
#include <asm/mipsmtregs.h>
#include <asm/system.h>
-static inline void unmask_mips_irq(unsigned int irq)
+static inline void unmask_mips_irq(struct irq_data *d)
{
- set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
+ set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_enable_hazard();
}
-static inline void mask_mips_irq(unsigned int irq)
+static inline void mask_mips_irq(struct irq_data *d)
{
- clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard();
}
static struct irq_chip mips_cpu_irq_controller = {
.name = "MIPS",
- .ack = mask_mips_irq,
- .mask = mask_mips_irq,
- .mask_ack = mask_mips_irq,
- .unmask = unmask_mips_irq,
- .eoi = unmask_mips_irq,
+ .irq_ack = mask_mips_irq,
+ .irq_mask = mask_mips_irq,
+ .irq_mask_ack = mask_mips_irq,
+ .irq_unmask = unmask_mips_irq,
+ .irq_eoi = unmask_mips_irq,
};
/*
@@ -65,13 +65,13 @@ static struct irq_chip mips_cpu_irq_controller = {
#define unmask_mips_mt_irq unmask_mips_irq
#define mask_mips_mt_irq mask_mips_irq
-static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
+static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
- unmask_mips_mt_irq(irq);
+ unmask_mips_mt_irq(d);
return 0;
}
@@ -80,22 +80,22 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
* While we ack the interrupt interrupts are disabled and thus we don't need
* to deal with concurrency issues. Same for mips_cpu_irq_end.
*/
-static void mips_mt_cpu_irq_ack(unsigned int irq)
+static void mips_mt_cpu_irq_ack(struct irq_data *d)
{
unsigned int vpflags = dvpe();
- clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
+ clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
- mask_mips_mt_irq(irq);
+ mask_mips_mt_irq(d);
}
static struct irq_chip mips_mt_cpu_irq_controller = {
.name = "MIPS",
- .startup = mips_mt_cpu_irq_startup,
- .ack = mips_mt_cpu_irq_ack,
- .mask = mask_mips_mt_irq,
- .mask_ack = mips_mt_cpu_irq_ack,
- .unmask = unmask_mips_mt_irq,
- .eoi = unmask_mips_mt_irq,
+ .irq_startup = mips_mt_cpu_irq_startup,
+ .irq_ack = mips_mt_cpu_irq_ack,
+ .irq_mask = mask_mips_mt_irq,
+ .irq_mask_ack = mips_mt_cpu_irq_ack,
+ .irq_unmask = unmask_mips_mt_irq,
+ .irq_eoi = unmask_mips_mt_irq,
};
void __init mips_cpu_irq_init(void)
--
1.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH RESEND 2/2] Alchemy: Convert to new irq methods.
2011-02-11 8:47 [PATCH RESEND 0/2] Alchemy: use new irq methods Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 1/2] MIPS: Convert to " Manuel Lauss
@ 2011-02-11 8:47 ` Manuel Lauss
1 sibling, 0 replies; 3+ messages in thread
From: Manuel Lauss @ 2011-02-11 8:47 UTC (permalink / raw)
To: Linux-MIPS; +Cc: Ralf Baechle, Manuel Lauss
Convert Alchemy core and board code to use new .irq_xxx methods.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
Run-tested on DB1200.
arch/mips/Kconfig | 1 +
arch/mips/alchemy/common/irq.c | 83 +++++++++++++++++++-----------------
arch/mips/alchemy/devboards/bcsr.c | 18 ++++----
3 files changed, 54 insertions(+), 48 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f5ecc05..401fc8f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -44,6 +44,7 @@ config MIPS_ALCHEMY
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
select SYS_SUPPORTS_ZBOOT
+ select GENERIC_HARDIRQS_NO_DEPRECATED
config AR7
bool "Texas Instruments AR7"
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 9f78ada..baef9a5 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -39,7 +39,7 @@
#include <asm/mach-pb1x00/pb1000.h>
#endif
-static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
+static int ic_settype(unsigned int irq, unsigned int flow_type);
/* NOTE on interrupt priorities: The original writers of this code said:
*
@@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
};
-static void au1x_ic0_unmask(unsigned int irq_nr)
+static void alchemy_ic0_unmask(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
au_writel(1 << bit, IC0_MASKSET);
au_writel(1 << bit, IC0_WAKESET);
au_sync();
}
-static void au1x_ic1_unmask(unsigned int irq_nr)
+static void alchemy_ic1_unmask(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
au_writel(1 << bit, IC1_MASKSET);
au_writel(1 << bit, IC1_WAKESET);
@@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
* nowhere in the current kernel sources is it disabled. --mlau
*/
#if defined(CONFIG_MIPS_PB1000)
- if (irq_nr == AU1000_GPIO15_INT)
+ if (d->irq == AU1000_GPIO15_INT)
au_writel(0x4000, PB1000_MDR); /* enable int */
#endif
au_sync();
}
-static void au1x_ic0_mask(unsigned int irq_nr)
+static void alchemy_ic0_mask(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
au_writel(1 << bit, IC0_MASKCLR);
au_writel(1 << bit, IC0_WAKECLR);
au_sync();
}
-static void au1x_ic1_mask(unsigned int irq_nr)
+static void alchemy_ic1_mask(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
au_writel(1 << bit, IC1_MASKCLR);
au_writel(1 << bit, IC1_WAKECLR);
au_sync();
}
-static void au1x_ic0_ack(unsigned int irq_nr)
+static void alchemy_ic0_ack(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
/*
* This may assume that we don't get interrupts from
@@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr)
au_sync();
}
-static void au1x_ic1_ack(unsigned int irq_nr)
+static void alchemy_ic1_ack(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
/*
* This may assume that we don't get interrupts from
@@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr)
au_sync();
}
-static void au1x_ic0_maskack(unsigned int irq_nr)
+static void alchemy_ic0_maskack(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
au_writel(1 << bit, IC0_WAKECLR);
au_writel(1 << bit, IC0_MASKCLR);
@@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr)
au_sync();
}
-static void au1x_ic1_maskack(unsigned int irq_nr)
+static void alchemy_ic1_maskack(struct irq_data *d)
{
- unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
+ unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
au_writel(1 << bit, IC1_WAKECLR);
au_writel(1 << bit, IC1_MASKCLR);
@@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
au_sync();
}
-static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
+static int alchemy_ic1_setwake(struct irq_data *d, unsigned int on)
{
- int bit = irq - AU1000_INTC1_INT_BASE;
+ int bit = d->irq - AU1000_INTC1_INT_BASE;
unsigned long wakemsk, flags;
/* only GPIO 0-7 can act as wakeup source. Fortunately these
@@ -330,30 +330,35 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
return 0;
}
+static int alchemy_ic_settype(struct irq_data *d, unsigned int flow_type)
+{
+ return ic_settype(d->irq, flow_type);
+}
+
/*
* irq_chips for both ICs; this way the mask handlers can be
* as short as possible.
*/
-static struct irq_chip au1x_ic0_chip = {
+static struct irq_chip alchemy_ic0_chip = {
.name = "Alchemy-IC0",
- .ack = au1x_ic0_ack,
- .mask = au1x_ic0_mask,
- .mask_ack = au1x_ic0_maskack,
- .unmask = au1x_ic0_unmask,
- .set_type = au1x_ic_settype,
+ .irq_ack = alchemy_ic0_ack,
+ .irq_mask = alchemy_ic0_mask,
+ .irq_mask_ack = alchemy_ic0_maskack,
+ .irq_unmask = alchemy_ic0_unmask,
+ .irq_set_type = alchemy_ic_settype,
};
-static struct irq_chip au1x_ic1_chip = {
+static struct irq_chip alchemy_ic1_chip = {
.name = "Alchemy-IC1",
- .ack = au1x_ic1_ack,
- .mask = au1x_ic1_mask,
- .mask_ack = au1x_ic1_maskack,
- .unmask = au1x_ic1_unmask,
- .set_type = au1x_ic_settype,
- .set_wake = au1x_ic1_setwake,
+ .irq_ack = alchemy_ic1_ack,
+ .irq_mask = alchemy_ic1_mask,
+ .irq_mask_ack = alchemy_ic1_maskack,
+ .irq_unmask = alchemy_ic1_unmask,
+ .irq_set_type = alchemy_ic_settype,
+ .irq_set_wake = alchemy_ic1_setwake,
};
-static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
+static int ic_settype(unsigned int irq, unsigned int flow_type)
{
struct irq_chip *chip;
unsigned long icr[6];
@@ -362,11 +367,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
if (irq >= AU1000_INTC1_INT_BASE) {
bit = irq - AU1000_INTC1_INT_BASE;
- chip = &au1x_ic1_chip;
+ chip = &alchemy_ic1_chip;
ic = 1;
} else {
bit = irq - AU1000_INTC0_INT_BASE;
- chip = &au1x_ic0_chip;
+ chip = &alchemy_ic0_chip;
ic = 0;
}
@@ -504,11 +509,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
*/
for (i = AU1000_INTC0_INT_BASE;
(i < AU1000_INTC0_INT_BASE + 32); i++)
- au1x_ic_settype(i, IRQ_TYPE_NONE);
+ ic_settype(i, IRQ_TYPE_NONE);
for (i = AU1000_INTC1_INT_BASE;
(i < AU1000_INTC1_INT_BASE + 32); i++)
- au1x_ic_settype(i, IRQ_TYPE_NONE);
+ ic_settype(i, IRQ_TYPE_NONE);
/*
* Initialize IC0, which is fixed per processor.
@@ -526,7 +531,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
au_writel(1 << bit, IC0_ASSIGNSET);
}
- au1x_ic_settype(irq_nr, map->im_type);
+ ic_settype(irq_nr, map->im_type);
++map;
}
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index c52af88..f91c43a 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
* CPLD generates tons of spurious interrupts (at least on my DB1200).
* -- mlau
*/
-static void bcsr_irq_mask(unsigned int irq_nr)
+static void bcsr_irq_mask(struct irq_data *d)
{
- unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+ unsigned short v = 1 << (d->irq - bcsr_csc_base);
__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
wmb();
}
-static void bcsr_irq_maskack(unsigned int irq_nr)
+static void bcsr_irq_maskack(struct irq_data *d)
{
- unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+ unsigned short v = 1 << (d->irq - bcsr_csc_base);
__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
wmb();
}
-static void bcsr_irq_unmask(unsigned int irq_nr)
+static void bcsr_irq_unmask(struct irq_data *d)
{
- unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+ unsigned short v = 1 << (d->irq - bcsr_csc_base);
__raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
wmb();
@@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr)
static struct irq_chip bcsr_irq_type = {
.name = "CPLD",
- .mask = bcsr_irq_mask,
- .mask_ack = bcsr_irq_maskack,
- .unmask = bcsr_irq_unmask,
+ .irq_mask = bcsr_irq_mask,
+ .irq_mask_ack = bcsr_irq_maskack,
+ .irq_unmask = bcsr_irq_unmask,
};
void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
--
1.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-02-11 8:48 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2011-02-11 8:47 [PATCH RESEND 0/2] Alchemy: use new irq methods Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 1/2] MIPS: Convert to " Manuel Lauss
2011-02-11 8:47 ` [PATCH RESEND 2/2] Alchemy: " Manuel Lauss
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