From: Tomi Valkeinen <tomi.valkeinen@ti.com>
To: "Turquette, Mike" <mturquette@ti.com>
Cc: "Taneja, Archit" <archit@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"Cousson, Benoit" <b-cousson@ti.com>
Subject: Re: [PATCH] OMAP: DSS2: Have separate irq handlers for DISPC and DSI
Date: Fri, 18 Feb 2011 11:50:50 +0200 [thread overview]
Message-ID: <1298022650.24062.20.camel@deskari> (raw)
In-Reply-To: <AANLkTik119ZB8+mR-MzXHUbZdxDo966HWehE8LeCxpWZ@mail.gmail.com>
On Fri, 2011-02-18 at 03:45 -0600, Turquette, Mike wrote:
<snip>
> PRM_IRQSTATUS_* registers will have status bits set even when the
> corresponding PRM_IRQENABLE_* bits are not set. The common assumption
> was that status bits would not be set if interrupts weren't enabled
> and this caused us some issues in prcm_interrupt_handler some time
> back. I don't know how DSS_IRQSTATUS works under the hood, but be
> careful of such assumptions :-)
That's how DISPC_IRQ* and DSI_IRQ* also works. But that's not what this
discussion was about =). DISPC and DSI have a shared interrupt line, and
there's a DSS_IRQSTATUS register with two bits, telling if the interrupt
was for DISPC or DSI.
Tomi
next prev parent reply other threads:[~2011-02-18 9:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-17 14:25 [PATCH] OMAP: DSS2: Have separate irq handlers for DISPC and DSI Archit Taneja
2011-02-18 9:10 ` Valkeinen, Tomi
2011-02-18 9:34 ` archit taneja
2011-02-18 9:45 ` Turquette, Mike
2011-02-18 9:50 ` Tomi Valkeinen [this message]
2011-02-18 10:25 ` archit taneja
2011-02-18 10:00 ` Tomi Valkeinen
2011-02-18 11:05 ` archit taneja
2011-02-18 11:11 ` Tomi Valkeinen
-- strict thread matches above, loose matches on Subject: below --
2011-02-21 6:00 Archit Taneja
2011-02-21 6:03 ` archit taneja
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