All of lore.kernel.org
 help / color / mirror / Atom feed
From: Artem Bityutskiy <dedekind1@gmail.com>
To: John Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	linux-mips@linux-mips.org, Ralph Hempel <ralph.hempel@lantiq.com>,
	linux-mtd@lists.infradead.org,
	Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH V2 06/10] MIPS: lantiq: add NOR flash support
Date: Mon, 07 Mar 2011 10:58:40 +0200	[thread overview]
Message-ID: <1299488320.2746.5.camel@localhost> (raw)
In-Reply-To: <1298996006-15960-7-git-send-email-blogic@openwrt.org>

On Tue, 2011-03-01 at 17:13 +0100, John Crispin wrote:
> NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described
> in the PCI patch, the EBU is a little buggy, resulting in the upper and lower
> 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2)
> 
> To work around this we do a addr^=2 during the probe. Once probed we adapt
> cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug.
> 
> Changes in V2
> * handle the endianess bug inside the map code and not in the generic cfi code
> * remove the addr swizzle patch
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> Cc: linux-mips@linux-mips.org
> Cc: linux-mtd@lists.infradead.org

There are a couple checkpatch.pl warnings, would you please address them
and resend?

-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)

WARNING: multiple messages have this Message-ID (diff)
From: Artem Bityutskiy <dedekind1@gmail.com>
To: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Ralph Hempel <ralph.hempel@lantiq.com>,
	linux-mtd@lists.infradead.org,
	Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH V2 06/10] MIPS: lantiq: add NOR flash support
Date: Mon, 07 Mar 2011 10:58:40 +0200	[thread overview]
Message-ID: <1299488320.2746.5.camel@localhost> (raw)
In-Reply-To: <1298996006-15960-7-git-send-email-blogic@openwrt.org>

On Tue, 2011-03-01 at 17:13 +0100, John Crispin wrote:
> NOR flash is attached to the same EBU (External Bus Unit) as PCI. As described
> in the PCI patch, the EBU is a little buggy, resulting in the upper and lower
> 16 bit of the data on a 32 bit read are swapped. (essentially we have a addr^=2)
> 
> To work around this we do a addr^=2 during the probe. Once probed we adapt
> cfi->addr_unlock1 and cfi->addr_unlock2 to represent the endianess bug.
> 
> Changes in V2
> * handle the endianess bug inside the map code and not in the generic cfi code
> * remove the addr swizzle patch
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
> Cc: linux-mips@linux-mips.org
> Cc: linux-mtd@lists.infradead.org

There are a couple checkpatch.pl warnings, would you please address them
and resend?

-- 
Best Regards,
Artem Bityutskiy (Артём Битюцкий)

  reply	other threads:[~2011-03-07  9:00 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-01 16:13 [PATCH V2 00/10] MIPS: add support for Lantiq SoCs John Crispin
2011-03-01 16:13 ` [PATCH V2 01/10] MIPS: lantiq: add initial " John Crispin
2011-03-01 16:13 ` [PATCH V2 02/10] MIPS: lantiq: add SoC specific code for XWAY family John Crispin
2011-03-01 16:13 ` [PATCH V2 03/10] MIPS: lantiq: add PCI controller support John Crispin
2011-03-01 16:13 ` [PATCH V2 04/10] MIPS: lantiq: add serial port support John Crispin
2011-03-01 16:13 ` [PATCH V2 05/10] MIPS: lantiq: add watchdog support John Crispin
2011-03-02 11:22   ` Sergei Shtylyov
2011-03-02 14:29     ` Ralf Baechle
2011-03-02 15:05       ` John Crispin
2011-03-02 16:27         ` Ralf Baechle
2011-03-02 17:36           ` Sergei Shtylyov
2011-03-02 17:34       ` Sergei Shtylyov
2011-03-02 15:44     ` John Crispin
2011-03-03 10:15     ` Jamie Iles
2011-03-03 11:21       ` Sergei Shtylyov
2011-03-01 16:13 ` [PATCH V2 06/10] MIPS: lantiq: add NOR flash support John Crispin
2011-03-01 16:13   ` John Crispin
2011-03-07  8:58   ` Artem Bityutskiy [this message]
2011-03-07  8:58     ` Artem Bityutskiy
2011-03-07 12:25     ` John Crispin
2011-03-07 12:25       ` John Crispin
2011-03-28 14:15       ` John Crispin
2011-03-28 14:15         ` John Crispin
2011-03-01 16:13 ` [PATCH V2 07/10] MIPS: lantiq: add platform device support John Crispin
2011-03-01 16:13 ` [PATCH V2 08/10] MIPS: lantiq: add mips_machine support John Crispin
2011-03-01 16:13 ` [PATCH V2 09/10] MIPS: lantiq: add machtypes for lantiq eval kits John Crispin
2011-03-01 16:13 ` [PATCH V2 10/10] MIPS: lantiq: add more gpio drivers John Crispin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1299488320.2746.5.camel@localhost \
    --to=dedekind1@gmail.com \
    --cc=blogic@openwrt.org \
    --cc=daniel.schwierzeck@googlemail.com \
    --cc=dwmw2@infradead.org \
    --cc=linux-mips@linux-mips.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=ralf@linux-mips.org \
    --cc=ralph.hempel@lantiq.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.