From: Heiko Stuebner <heiko@sntech.de>
To: Elaine Zhang <zhangqing@rock-chips.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com,
Finley Xiao <finley.xiao@rock-chips.com>
Subject: Re: [PATCH v2 3/6] clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
Date: Fri, 14 Jun 2019 12:44:02 +0200 [thread overview]
Message-ID: <130046083.dVx6RxQuTH@phil> (raw)
In-Reply-To: <1557991736-13580-4-git-send-email-zhangqing@rock-chips.com>
Am Donnerstag, 16. Mai 2019, 09:28:53 CEST schrieb Elaine Zhang:
> From: Finley Xiao <finley.xiao@rock-chips.com>
>
> The div offset of some clocks are different from their mux offset
> and the COMPOSITE clock-type require that div and mux offset are
> the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.
>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
already applied that one from the v1 series.
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: Elaine Zhang <zhangqing@rock-chips.com>
Cc: huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com,
sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
Finley Xiao <finley.xiao@rock-chips.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/6] clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
Date: Fri, 14 Jun 2019 12:44:02 +0200 [thread overview]
Message-ID: <130046083.dVx6RxQuTH@phil> (raw)
In-Reply-To: <1557991736-13580-4-git-send-email-zhangqing@rock-chips.com>
Am Donnerstag, 16. Mai 2019, 09:28:53 CEST schrieb Elaine Zhang:
> From: Finley Xiao <finley.xiao@rock-chips.com>
>
> The div offset of some clocks are different from their mux offset
> and the COMPOSITE clock-type require that div and mux offset are
> the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.
>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
already applied that one from the v1 series.
Heiko
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next prev parent reply other threads:[~2019-06-14 10:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 7:28 [PATCH v2 0/6] clk: rockchip: Support for some new features Elaine Zhang
2019-05-16 7:28 ` Elaine Zhang
2019-05-16 7:28 ` [PATCH v2 1/6] clk: rockchip: Add supprot to limit input rate for fractional divider Elaine Zhang
2019-05-16 7:28 ` Elaine Zhang
2019-05-16 7:28 ` [PATCH v2 2/6] clk: rockchip: fix up the frac clk get rate error Elaine Zhang
2019-05-16 7:28 ` Elaine Zhang
2019-05-16 7:28 ` [PATCH v2 3/6] clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type Elaine Zhang
2019-05-16 7:28 ` Elaine Zhang
2019-06-14 10:44 ` Heiko Stuebner [this message]
2019-06-14 10:44 ` Heiko Stuebner
2019-05-16 7:28 ` [PATCH v2 4/6] clk: rockchip: add a clock-type for muxes based in the pmugrf Elaine Zhang
2019-05-16 7:28 ` Elaine Zhang
2019-05-16 7:29 ` [PATCH v2 5/6] clk: rockchip: add pll up and down when change pll freq Elaine Zhang
2019-05-16 7:29 ` Elaine Zhang
2019-05-16 7:30 ` [PATCH v2 6/6] clk: rockchip: support pll setting by auto Elaine Zhang
2019-05-16 7:30 ` Elaine Zhang
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