[Qemu-devel] [RFC 22/28] target-xtensa: implement extended L32R

[Max Filippov <jcmvbkbc@gmail.com>]

See ISA, 4.3.3 for details.

Enable bit of LITBASE may be stored separately for further speedup.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target-xtensa/cpu.h       |    1 +
 target-xtensa/helper.c    |    1 +
 target-xtensa/translate.c |   18 ++++++++++++++++--
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 7fade0c..8110665 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -110,6 +110,7 @@ enum {
     LEND = 1,
     LCOUNT = 2,
     SAR = 3,
+    LITBASE = 5,
     SCOMPARE1 = 12,
     WINDOW_BASE = 72,
     WINDOW_START = 73,
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 61d1ab3..6df2e50 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -38,6 +38,7 @@ void cpu_reset(CPUXtensaState *env)
 {
     env->exception_taken = 0;
     env->pc = env->config->exception_vector[EXC_RESET];
+    env->sregs[LITBASE] &= ~1;
     env->sregs[PS] = 0x1f;
 }
 
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index e33c2fa..53e0d02 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -62,6 +62,7 @@ static const char * const sregnames[256] = {
     [LEND] = "LEND",
     [LCOUNT] = "LCOUNT",
     [SAR] = "SAR",
+    [LITBASE] = "LITBASE",
     [SCOMPARE1] = "SCOMPARE1",
     [WINDOW_BASE] = "WINDOW_BASE",
     [WINDOW_START] = "WINDOW_START",
@@ -1168,12 +1169,25 @@ static void disas_xtensa_insn(DisasContext *dc)
 
     case 1: /*L32R*/
         {
-            TCGv_i32 tmp = tcg_const_i32(
+            TCGv_i32 tmp = tcg_temp_local_new_i32();
+
+            tcg_gen_movi_i32(tmp,
                     (0xfffc0000 | (RI16_IMM16 << 2)) +
                     ((dc->pc + 3) & ~3));
 
-            /* no ext L32R */
+            if (option_enabled(dc, XTENSA_OPTION_EXTENDED_L32R)) {
+                TCGv_i32 tmp1 = tcg_temp_new_i32();
+                int label = gen_new_label();
+
+                tcg_gen_andi_i32(tmp1, cpu_SR[LITBASE], 1);
+                tcg_gen_brcondi_i32(TCG_COND_EQ, tmp1, 0, label);
+                tcg_gen_andi_i32(tmp1, cpu_SR[LITBASE], 0xfffff000);
+                tcg_gen_addi_i32(tmp, tmp1, (0xfffc0000 | (RI16_IMM16 << 2)));
+                gen_set_label(label);
+                tcg_temp_free(tmp1);
+            }
 
+            /* much simplified, no MMU */
             tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
             tcg_temp_free(tmp);
         }
-- 
1.7.3.4