From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
Stephane Eranian <eranian@google.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/4] perf, x86: Add Intel SandyBridge pricise store support
Date: Mon, 11 Jul 2011 10:52:17 +0200 [thread overview]
Message-ID: <1310374337.13309.28.camel@twins> (raw)
In-Reply-To: <1310374633.18875.218.camel@minggr.sh.intel.com>
On Mon, 2011-07-11 at 16:57 +0800, Lin Ming wrote:
> On Mon, 2011-07-11 at 16:32 +0800, Peter Zijlstra wrote:
> > On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> > > Implements Intel memory store event for SandyBridge.
> > >
> > > $ perf mem -t store record make -j8
> >
> >
> > I was just looking through the Intel SDM, and stumbled upon:
> >
> > C0H 01H INST_RETIRED.PREC_DIST
> >
> > Precise instruction retired event
> > with HW to reduce effect of PEBS
> > shadow in IP distribution PMC1 only;
> > Must quiesce other PMCs.
> > ^^^^^^^^^^^^^^^^^^^^^^^^
> >
> > WTF!? Are they real? The implementation as provided by you doesn't do
> > that (quite understandably), but please check with the hardware folks.
>
> This is Precise Distribution of Instructions Retired (PDIR), which is
> not related to Precise Store.
Gah right, still ridiculous constraint.
next prev parent reply other threads:[~2011-07-11 8:52 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-04 8:02 [PATCH 0/4] perf: memory load/store events generalization Lin Ming
2011-07-04 8:02 ` [PATCH 1/4] perf: Add memory load/store events generic code Lin Ming
2011-07-04 8:33 ` Peter Zijlstra
2011-07-04 8:44 ` Peter Zijlstra
2011-07-05 12:03 ` Peter Zijlstra
2011-07-05 23:02 ` Paul Mackerras
2011-07-06 13:58 ` Peter Zijlstra
2011-07-08 7:18 ` Anton Blanchard
2011-07-08 15:18 ` Peter Zijlstra
2011-08-08 11:57 ` Peter Zijlstra
2011-08-08 11:59 ` Peter Zijlstra
2011-07-04 22:01 ` Andi Kleen
2011-07-05 8:43 ` Peter Zijlstra
2011-07-04 11:08 ` Peter Zijlstra
2011-07-04 11:16 ` Peter Zijlstra
2011-07-04 21:52 ` Andi Kleen
2011-07-05 11:54 ` Lin Ming
2011-07-05 14:17 ` Peter Zijlstra
2011-07-06 5:53 ` Lin Ming
2011-07-06 13:51 ` Peter Zijlstra
2011-07-07 2:01 ` Lin Ming
2011-07-04 8:02 ` [PATCH 2/4] perf, x86: Add Intel Nhm/Wsm/Snb load latency support Lin Ming
2011-07-05 13:17 ` Peter Zijlstra
2011-07-05 13:34 ` Lin Ming
2011-07-22 18:58 ` Stephane Eranian
2011-07-04 8:02 ` [PATCH 3/4] perf, x86: Add Intel SandyBridge pricise store support Lin Ming
2011-07-11 8:32 ` Peter Zijlstra
2011-07-11 8:57 ` Lin Ming
2011-07-11 8:52 ` Peter Zijlstra [this message]
2011-07-04 8:02 ` [PATCH 4/4] perf, tool: Add new command "perf mem" Lin Ming
2011-07-04 22:00 ` Andi Kleen
2011-07-05 1:35 ` Lin Ming
2011-07-22 18:55 ` [PATCH 0/4] perf: memory load/store events generalization Stephane Eranian
2011-07-22 21:01 ` Andi Kleen
2011-07-22 21:14 ` Stephane Eranian
2011-07-22 21:43 ` Andi Kleen
2011-07-22 21:59 ` Stephane Eranian
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