From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Scott Wood <scottwood@freescale.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>,
Alexander Graf <agraf@suse.de>, kvm <kvm@vger.kernel.org>,
qemu-devel Developers <qemu-devel@nongnu.org>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
David Gibson <dwg@au1.ibm.com>
Subject: Re: qemu-kvm: Role of flush_icache_range on PPC
Date: Thu, 29 Sep 2011 07:02:35 +1000 [thread overview]
Message-ID: <1317243755.29415.99.camel@pasglop> (raw)
In-Reply-To: <4E8358FD.6030408@freescale.com>
On Wed, 2011-09-28 at 12:27 -0500, Scott Wood wrote:
> Why would it need to be synchronous? Even if it's asynchronous emulated
> DMA, we don't want it sitting around only in a data cache that
> instruction fetches won't snoop.
Except that this is exactly what happens on real HW :-)
The guest will do the necessary invalidations. DMA doesn't keep the
icache coherent on HW, why should it on kvm/qemu ?
> It's not implemented yet in mainline for powerpc (we have something
> internal that is on the backlog of things to be cleaned up and sent
> out), but this is what we'd do for kvm_arch_insert_sw_breakpoint().
Yes, breakpoints do need a flash, as does the initial program load.
Cheers,
Ben.
WARNING: multiple messages have this Message-ID (diff)
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Scott Wood <scottwood@freescale.com>
Cc: kvm <kvm@vger.kernel.org>,
qemu-devel Developers <qemu-devel@nongnu.org>,
Jan Kiszka <jan.kiszka@siemens.com>,
Alexander Graf <agraf@suse.de>, David Gibson <dwg@au1.ibm.com>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>
Subject: Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC
Date: Thu, 29 Sep 2011 07:02:35 +1000 [thread overview]
Message-ID: <1317243755.29415.99.camel@pasglop> (raw)
In-Reply-To: <4E8358FD.6030408@freescale.com>
On Wed, 2011-09-28 at 12:27 -0500, Scott Wood wrote:
> Why would it need to be synchronous? Even if it's asynchronous emulated
> DMA, we don't want it sitting around only in a data cache that
> instruction fetches won't snoop.
Except that this is exactly what happens on real HW :-)
The guest will do the necessary invalidations. DMA doesn't keep the
icache coherent on HW, why should it on kvm/qemu ?
> It's not implemented yet in mainline for powerpc (we have something
> internal that is on the backlog of things to be cleaned up and sent
> out), but this is what we'd do for kvm_arch_insert_sw_breakpoint().
Yes, breakpoints do need a flash, as does the initial program load.
Cheers,
Ben.
next prev parent reply other threads:[~2011-09-28 21:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-28 14:23 qemu-kvm: Role of flush_icache_range on PPC Jan Kiszka
2011-09-28 14:23 ` [Qemu-devel] " Jan Kiszka
2011-09-28 14:26 ` Alexander Graf
2011-09-28 14:26 ` [Qemu-devel] " Alexander Graf
2011-09-28 14:45 ` Jan Kiszka
2011-09-28 14:45 ` [Qemu-devel] " Jan Kiszka
2011-09-28 14:49 ` Jan Kiszka
2011-09-28 14:49 ` [Qemu-devel] " Jan Kiszka
2011-09-28 14:57 ` Alexander Graf
2011-09-28 14:57 ` [Qemu-devel] " Alexander Graf
2011-09-28 17:27 ` Scott Wood
2011-09-28 17:27 ` [Qemu-devel] " Scott Wood
2011-09-28 21:02 ` Benjamin Herrenschmidt [this message]
2011-09-28 21:02 ` Benjamin Herrenschmidt
2011-09-28 21:20 ` Scott Wood
2011-09-28 21:20 ` [Qemu-devel] " Scott Wood
2011-09-28 21:34 ` Benjamin Herrenschmidt
2011-09-28 21:34 ` [Qemu-devel] " Benjamin Herrenschmidt
2011-09-28 20:58 ` Benjamin Herrenschmidt
2011-09-28 20:58 ` [Qemu-devel] " Benjamin Herrenschmidt
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