Flashing host SPI NOR

Flashing host SPI NOR

[Aaron Williams]

Hi all,

I've run into a problem when it comes to flashing our host SPI NOR. If I boot 
our host then the SPI NOR is put in a different mode and I am unable to write 
to it from OpenBMC. The only way I can update our host SPI NOR is if I first 
power down the host then reboot OpenBMC. Is there some way I can force OpenBMC 
to re-initialize the SPI NOR before writing to it? I can read from the SPI nor 
just fine from the BMC after the host has accessed it, I just can't erase or 
write to it without everything getting corrupted. The device is a Macronix 
MX25L25645GMI-08G. Note that on the host side we are using QREAD and 4PP mode 
and 4 bit mode whereas for OpenBMC we only have 1 bit mode wired up. 

Ideally I'd love to be able to make use of the GPIO arbitration we have 
between the host and the BMC. We have two GPIO pins, one where the host 
requests access to the SPI NOR and the other where the BMC grants access.

-Aaron

Re: Flashing host SPI NOR

[Cédric Le Goater]

Hello,

On 1/24/19 11:09 AM, Aaron Williams wrote:
> Hi all,
> 
> I've run into a problem when it comes to flashing our host SPI NOR. If I boot 
> our host then the SPI NOR is put in a different mode and I am unable to write 
> to it from OpenBMC. The only way I can update our host SPI NOR is if I first 
> power down the host then reboot OpenBMC. Is there some way I can force OpenBMC 
> to re-initialize the SPI NOR before writing to it? I can read from the SPI nor 
> just fine from the BMC after the host has accessed it, I just can't erase or 
> write to it without everything getting corrupted. The device is a Macronix 
> MX25L25645GMI-08G. Note that on the host side we are using QREAD and 4PP mode 
> and 4 bit mode whereas for OpenBMC we only have 1 bit mode wired up. 

Could you give us a little more information on the platform, host and BMC ? 

which host FW and version ? Which version of OpenBMC ?

Thanks,

C.  
  

> Ideally I'd love to be able to make use of the GPIO arbitration we have 
> between the host and the BMC. We have two GPIO pins, one where the host 
> requests access to the SPI NOR and the other where the BMC grants access.
> 
> -Aaron
> 
>