From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>,
Keith Packard <keithp@keithp.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: Benson Leung <bleung@chromium.org>,
Yufeng Shen <miletus@chromium.org>,
Daniel Kurtz <djkurtz@chromium.org>
Subject: Re: [PATCH 4/7 v6] drm/i915/intel_i2c: use WAIT cycle, not STOP
Date: Wed, 28 Mar 2012 19:48:51 +0100 [thread overview]
Message-ID: <1332960542_131144@CP5-2952> (raw)
In-Reply-To: <1332959199-32161-5-git-send-email-djkurtz@chromium.org>
On Thu, 29 Mar 2012 02:26:36 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
> The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
> transaction) during a DATA or WAIT phase. In other words, the
> controller rejects a STOP requested as part of the first transaction in a
> sequence.
The original docs have "this can only cause a STOP to be generated if a
GMBUS cycle is generated, the GMBUS is currently in a data phase, or it
is in a WAIT phase."
So from that it seems STOP | INDEX? | WAIT is always a valid
combination and is explicitly listed in the register set.
I defer to actual testing though ;)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Kurtz <djkurtz@chromium.org>,
Daniel Vetter <daniel@ffwll.ch>,
Keith Packard <keithp@keithp.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: Benson Leung <bleung@chromium.org>,
Yufeng Shen <miletus@chromium.org>,
Daniel Kurtz <djkurtz@chromium.org>
Subject: Re: [PATCH 4/7 v6] drm/i915/intel_i2c: use WAIT cycle, not STOP
Date: Wed, 28 Mar 2012 19:48:51 +0100 [thread overview]
Message-ID: <1332960542_131144@CP5-2952> (raw)
In-Reply-To: <1332959199-32161-5-git-send-email-djkurtz@chromium.org>
On Thu, 29 Mar 2012 02:26:36 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
> The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
> transaction) during a DATA or WAIT phase. In other words, the
> controller rejects a STOP requested as part of the first transaction in a
> sequence.
The original docs have "this can only cause a STOP to be generated if a
GMBUS cycle is generated, the GMBUS is currently in a data phase, or it
is in a WAIT phase."
So from that it seems STOP | INDEX? | WAIT is always a valid
combination and is explicitly listed in the register set.
I defer to actual testing though ;)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-03-28 18:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-28 18:26 [PATCH 0/7 v6] fix gmbus writes and related issues Daniel Kurtz
2012-03-28 18:26 ` [PATCH 1/7 v6] drm/i915/intel_i2c: handle zero-length writes Daniel Kurtz
2012-03-28 18:34 ` Chris Wilson
2012-03-28 18:34 ` Chris Wilson
2012-03-28 18:26 ` [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes Daniel Kurtz
2012-03-28 18:41 ` Chris Wilson
2012-03-28 18:41 ` Chris Wilson
2012-03-29 8:46 ` Daniel Kurtz
2012-03-29 9:15 ` Daniel Vetter
2012-03-28 18:26 ` [PATCH 3/7 v6] drm/i915/intel_i2c: always wait for IDLE before clearing NAK Daniel Kurtz
2012-03-28 18:26 ` [PATCH 4/7 v6] drm/i915/intel_i2c: use WAIT cycle, not STOP Daniel Kurtz
2012-03-28 18:48 ` Chris Wilson [this message]
2012-03-28 18:48 ` Chris Wilson
2012-03-29 8:39 ` Daniel Kurtz
2012-03-28 18:26 ` [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Daniel Kurtz
2012-03-28 18:52 ` Chris Wilson
2012-03-28 18:52 ` Chris Wilson
2012-03-29 8:37 ` Daniel Kurtz
2012-03-29 9:25 ` Daniel Vetter
2012-03-28 18:26 ` [PATCH 6/7 v6] drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop Daniel Kurtz
2012-03-28 18:53 ` Chris Wilson
2012-03-28 18:53 ` Chris Wilson
2012-03-28 18:26 ` [PATCH 7/7 v6] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers Daniel Kurtz
2012-03-28 18:53 ` Chris Wilson
2012-03-28 18:53 ` Chris Wilson
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