From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Kurtz <djkurtz@chromium.org>Daniel Kurtz
<djkurtz@chromium.org>, Keith Packard <keithp@keithp.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Benson Leung <bleung@chromium.org>,
Yufeng Shen <miletus@chromium.org>
Subject: Re: [PATCH 4/8 v7] drm/i915/intel_i2c: use WAIT cycle, not STOP
Date: Wed, 11 Apr 2012 21:28:47 +0100 [thread overview]
Message-ID: <1334176129_372754@CP5-2952> (raw)
In-Reply-To: <CAGS+omD9dTTK4gRERy406nLFEMfqC=hw6ZFe3_V9yacSR2r9Sw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 666 bytes --]
On Thu, 12 Apr 2012 02:16:45 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
> On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > - Chris Wilson suggested on irc that we should wait for HW_READY even for
> > Â zero-length writes (and also reads), currently we don't.
>
> I don't think so. We just need to wait for (GMBUS_SATOER |
> GMBUS_HW_WAIT_PHASE).
> Why would we wait for HW_READY, too?
Just paranoia when looking at the read/write sequences and wondering how
safe they were with 0-length read/writes. No real reason to suspect that
the code is incorrect in any way.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Kurtz <djkurtz@chromium.org>,
Daniel Kurtz <djkurtz@chromium.org>,
Keith Packard <keithp@keithp.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Benson Leung <bleung@chromium.org>,
Yufeng Shen <miletus@chromium.org>
Subject: Re: [PATCH 4/8 v7] drm/i915/intel_i2c: use WAIT cycle, not STOP
Date: Wed, 11 Apr 2012 21:28:47 +0100 [thread overview]
Message-ID: <1334176129_372754@CP5-2952> (raw)
In-Reply-To: <CAGS+omD9dTTK4gRERy406nLFEMfqC=hw6ZFe3_V9yacSR2r9Sw@mail.gmail.com>
On Thu, 12 Apr 2012 02:16:45 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
> On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > - Chris Wilson suggested on irc that we should wait for HW_READY even for
> > zero-length writes (and also reads), currently we don't.
>
> I don't think so. We just need to wait for (GMBUS_SATOER |
> GMBUS_HW_WAIT_PHASE).
> Why would we wait for HW_READY, too?
Just paranoia when looking at the read/write sequences and wondering how
safe they were with 0-length read/writes. No real reason to suspect that
the code is incorrect in any way.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-04-11 20:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-30 11:46 [PATCH 0/8 v7] fix gmbus writes and related issues Daniel Kurtz
2012-03-30 11:46 ` [PATCH 1/8 v7] drm/i915/intel_i2c: handle zero-length writes Daniel Kurtz
2012-04-03 22:54 ` Chris Wilson
2012-04-03 22:54 ` Chris Wilson
2012-03-30 11:46 ` [PATCH 2/8 v7] drm/i915/intel_i2c: use double-buffered writes Daniel Kurtz
2012-03-30 11:46 ` [PATCH 3/8 v7] drm/i915/intel_i2c: always wait for IDLE before clearing NAK Daniel Kurtz
2012-03-30 11:46 ` [PATCH 4/8 v7] drm/i915/intel_i2c: use WAIT cycle, not STOP Daniel Kurtz
2012-04-10 10:37 ` Daniel Vetter
2012-04-10 10:41 ` Daniel Vetter
2012-04-10 10:56 ` Daniel Kurtz
2012-04-10 15:03 ` Daniel Vetter
2012-04-10 21:34 ` Chris Wilson
2012-04-10 21:34 ` Chris Wilson
2012-04-11 18:17 ` Daniel Kurtz
2012-04-11 20:26 ` Chris Wilson
2012-04-11 20:26 ` Chris Wilson
2012-04-13 11:49 ` Daniel Kurtz
2012-04-11 18:16 ` Daniel Kurtz
2012-04-11 20:04 ` Daniel Vetter
2012-04-11 20:28 ` Chris Wilson [this message]
2012-04-11 20:28 ` Chris Wilson
2012-03-30 11:46 ` [PATCH 5/8 v7] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Daniel Kurtz
2012-03-30 11:46 ` [PATCH 6/8 v7] drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop Daniel Kurtz
2012-03-30 11:46 ` [PATCH 7/8 v7] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers Daniel Kurtz
2012-03-30 11:46 ` [PATCH 8/8 v7] drm/i915/intel_i2c: use DRM_ERROR on timeouts Daniel Kurtz
2012-03-30 12:49 ` [PATCH 0/8 v7] fix gmbus writes and related issues Chris Wilson
2012-03-30 12:49 ` Chris Wilson
2012-03-30 15:33 ` Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1334176129_372754@CP5-2952 \
--to=chris@chris-wilson.co.uk \
--cc=djkurtz@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.