* [PATCH v4] drm/i915: rc6 in sysfs
@ 2012-04-11 4:17 Ben Widawsky
2012-04-11 8:14 ` Chris Wilson
0 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2012-04-11 4:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky, f, Daniel Vetter, Ben Widawsky, Arjan van de Ven
Merge rc6 information into the power group for our device. Until now the
i915 driver has not had any sysfs entries (aside from the connector
stuff enabled by drm core). Since it seems like we're likely to have
more in the future I created a new file for sysfs stubs, as well as the
rc6 sysfs functions which don't really belong elsewhere (perhaps
i915_suspend, but most of the stuff is in intel_display,c).
displays rc6 modes enabled (as a hex mask):
cat /sys/class/drm/card0/power/rc6_enable
displays #ms GPU has been in rc6 since boot:
cat /sys/class/drm/card0/power/rc6_residency_ms
displays #ms GPU has been in deep rc6 since boot:
cat /sys/class/drm/card0/power/rc6p_residency_ms
displays #ms GPU has been in deepest rc6 since boot:
cat /sys/class/drm/card0/power/rc6pp_residency_ms
Important note: I've seen on SNB that even when RC6 is *not* enabled the
rc6 register seems to have a random value in it. I can only guess at the
reason reason for this. Those writing tools that utilize this value need
to be careful and probably want to scrutinize the value very carefully.
v2: use common rc6 residency units to milliseconds for the other RC6 types
v3: don't create sysfs files for GEN <= 5
add a rc6_enable to show a mask of enabled rc6 types
use unmerge instead of remove for sysfs group
squash intel_enable_rc6() extraction into this patch
v4: rename sysfs files (Chris)
CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>f
CC: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_dma.c | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_sysfs.c | 113 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 2 +-
5 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_sysfs.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ce7fc77..f801330 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -12,6 +12,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
i915_gem_execbuffer.o \
i915_gem_gtt.o \
i915_gem_tiling.o \
+ i915_sysfs.o \
i915_trace_points.o \
intel_display.o \
intel_crt.o \
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 652f43f..333b746 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2139,6 +2139,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
}
}
+ i915_setup_sysfs(dev);
+
/* Must be done after probing outputs */
intel_opregion_init(dev);
acpi_video_register();
@@ -2190,6 +2192,8 @@ int i915_driver_unload(struct drm_device *dev)
i915_mch_dev = NULL;
spin_unlock(&mchdev_lock);
+ i915_teardown_sysfs(dev);
+
if (dev_priv->mm.inactive_shrinker.shrink)
unregister_shrinker(&dev_priv->mm.inactive_shrinker);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dcdccb..a189f75 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1385,6 +1385,10 @@ extern int i915_restore_state(struct drm_device *dev);
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
+/* i915_sysfs.c */
+void i915_setup_sysfs(struct drm_device *dev_priv);
+void i915_teardown_sysfs(struct drm_device *dev_priv);
+
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
@@ -1441,6 +1445,7 @@ extern void ironlake_enable_rc6(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
+extern int intel_enable_rc6(const struct drm_device *dev);
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
new file mode 100644
index 0000000..2319f06
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ben Widawsky <ben@bwidawsk.net>
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/stat.h>
+#include <linux/sysfs.h>
+#include "i915_drv.h"
+
+static u32 calc_residency(struct drm_device *dev, const u32 reg)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u64 raw_time; /* 32b value may overflow during fixed point math */
+ u32 residency;
+
+ if (!intel_enable_rc6(dev))
+ return 0;
+
+ raw_time = I915_READ(reg) * 128ULL;
+ residency = DIV_ROUND_CLOSEST(raw_time, 1000) / 100;
+ return residency;
+}
+
+static ssize_t
+show_rc6_mask(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ return snprintf(buf, PAGE_SIZE, "%x", intel_enable_rc6(dminor->dev));
+}
+
+static ssize_t
+show_rc6_ms(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
+ return snprintf(buf, PAGE_SIZE, "%u", rc6_residency);
+}
+
+static ssize_t
+show_rc6p_ms(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
+ return snprintf(buf, PAGE_SIZE, "%u", rc6p_residency);
+}
+
+static ssize_t
+show_rc6pp_ms(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+ u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
+ return snprintf(buf, PAGE_SIZE, "%u", rc6pp_residency);
+}
+
+static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
+static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
+static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
+static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
+
+static struct attribute *rc6_attrs[] = {
+ &dev_attr_rc6_enable.attr,
+ &dev_attr_rc6_residency_ms.attr,
+ &dev_attr_rc6p_residency_ms.attr,
+ &dev_attr_rc6pp_residency_ms.attr,
+ NULL
+};
+
+static struct attribute_group rc6_attr_group = {
+ .name = power_group_name,
+ .attrs = rc6_attrs
+};
+
+void i915_setup_sysfs(struct drm_device *dev)
+{
+ int ret;
+
+ /* ILK doesn't have any residency information */
+ if (INTEL_INFO(dev)->gen < 6)
+ return;
+
+ ret = sysfs_merge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
+ if (ret)
+ DRM_ERROR("sysfs setup failed\n");
+}
+
+void i915_teardown_sysfs(struct drm_device *dev)
+{
+ sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
+}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42dbe14..5b8b3d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8547,7 +8547,7 @@ void intel_init_emon(struct drm_device *dev)
dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
}
-static int intel_enable_rc6(struct drm_device *dev)
+int intel_enable_rc6(const struct drm_device *dev)
{
/*
* Respect the kernel parameter if it is set
--
1.7.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: rc6 in sysfs
2012-04-11 4:17 [PATCH v4] drm/i915: rc6 in sysfs Ben Widawsky
@ 2012-04-11 8:14 ` Chris Wilson
2012-04-11 9:51 ` Daniel Vetter
2012-04-11 22:10 ` Chris Wilson
0 siblings, 2 replies; 5+ messages in thread
From: Chris Wilson @ 2012-04-11 8:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Ben Widawsky, f, Arjan van de Ven, Ben Widawsky
On Tue, 10 Apr 2012 21:17:01 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> Merge rc6 information into the power group for our device. Until now the
> i915 driver has not had any sysfs entries (aside from the connector
> stuff enabled by drm core). Since it seems like we're likely to have
> more in the future I created a new file for sysfs stubs, as well as the
> rc6 sysfs functions which don't really belong elsewhere (perhaps
> i915_suspend, but most of the stuff is in intel_display,c).
>
> displays rc6 modes enabled (as a hex mask):
> cat /sys/class/drm/card0/power/rc6_enable
>
> displays #ms GPU has been in rc6 since boot:
> cat /sys/class/drm/card0/power/rc6_residency_ms
>
> displays #ms GPU has been in deep rc6 since boot:
> cat /sys/class/drm/card0/power/rc6p_residency_ms
>
> displays #ms GPU has been in deepest rc6 since boot:
> cat /sys/class/drm/card0/power/rc6pp_residency_ms
>
> Important note: I've seen on SNB that even when RC6 is *not* enabled the
> rc6 register seems to have a random value in it. I can only guess at the
> reason reason for this. Those writing tools that utilize this value need
> to be careful and probably want to scrutinize the value very carefully.
>
> v2: use common rc6 residency units to milliseconds for the other RC6 types
>
> v3: don't create sysfs files for GEN <= 5
> add a rc6_enable to show a mask of enabled rc6 types
> use unmerge instead of remove for sysfs group
> squash intel_enable_rc6() extraction into this patch
>
> v4: rename sysfs files (Chris)
>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> CC: Daniel Vetter <daniel.vetter@ffwll.ch>f
> CC: Arjan van de Ven <arjan@linux.intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
So the only downside to using the pre-existing power group is that we do
not get the interface if power-management is compiled out of the kernel,
which I suppose is appropriate.
I'm down to just bikeshedding over useless lines of code which do not
even add visual clarity...
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: rc6 in sysfs
2012-04-11 8:14 ` Chris Wilson
@ 2012-04-11 9:51 ` Daniel Vetter
2012-04-11 22:10 ` Chris Wilson
1 sibling, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2012-04-11 9:51 UTC (permalink / raw)
To: Chris Wilson
Cc: Ben Widawsky, f, Daniel Vetter, intel-gfx, Ben Widawsky,
Arjan van de Ven
On Wed, Apr 11, 2012 at 09:14:43AM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 21:17:01 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> > Merge rc6 information into the power group for our device. Until now the
> > i915 driver has not had any sysfs entries (aside from the connector
> > stuff enabled by drm core). Since it seems like we're likely to have
> > more in the future I created a new file for sysfs stubs, as well as the
> > rc6 sysfs functions which don't really belong elsewhere (perhaps
> > i915_suspend, but most of the stuff is in intel_display,c).
> >
> > displays rc6 modes enabled (as a hex mask):
> > cat /sys/class/drm/card0/power/rc6_enable
> >
> > displays #ms GPU has been in rc6 since boot:
> > cat /sys/class/drm/card0/power/rc6_residency_ms
> >
> > displays #ms GPU has been in deep rc6 since boot:
> > cat /sys/class/drm/card0/power/rc6p_residency_ms
> >
> > displays #ms GPU has been in deepest rc6 since boot:
> > cat /sys/class/drm/card0/power/rc6pp_residency_ms
> >
> > Important note: I've seen on SNB that even when RC6 is *not* enabled the
> > rc6 register seems to have a random value in it. I can only guess at the
> > reason reason for this. Those writing tools that utilize this value need
> > to be careful and probably want to scrutinize the value very carefully.
> >
> > v2: use common rc6 residency units to milliseconds for the other RC6 types
> >
> > v3: don't create sysfs files for GEN <= 5
> > add a rc6_enable to show a mask of enabled rc6 types
> > use unmerge instead of remove for sysfs group
> > squash intel_enable_rc6() extraction into this patch
> >
> > v4: rename sysfs files (Chris)
> >
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > CC: Daniel Vetter <daniel.vetter@ffwll.ch>f
> > CC: Arjan van de Ven <arjan@linux.intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>
> So the only downside to using the pre-existing power group is that we do
> not get the interface if power-management is compiled out of the kernel,
> which I suppose is appropriate.
>
> I'm down to just bikeshedding over useless lines of code which do not
> even add visual clarity...
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: rc6 in sysfs
2012-04-11 8:14 ` Chris Wilson
2012-04-11 9:51 ` Daniel Vetter
@ 2012-04-11 22:10 ` Chris Wilson
2012-04-11 22:37 ` Daniel Vetter
1 sibling, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2012-04-11 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Ben Widawsky, f, Arjan van de Ven, Ben Widawsky
On Wed, 11 Apr 2012 09:14:43 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> I'm down to just bikeshedding over useless lines of code which do not
> even add visual clarity...
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Oops, need to learn to spot 64-bit divides which become an issue on
32-bit builds.
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2319f06..f1b5108 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -35,14 +35,12 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u64 raw_time; /* 32b value may overflow during fixed point math */
- u32 residency;
if (!intel_enable_rc6(dev))
return 0;
- raw_time = I915_READ(reg) * 128ULL;
- residency = DIV_ROUND_CLOSEST(raw_time, 1000) / 100;
- return residency;
+ raw_time = I915_READ(reg) * 128ULL + 500;
+ return do_div(raw_time, 100000);
}
static ssize_t
--
1.7.9.5
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4] drm/i915: rc6 in sysfs
2012-04-11 22:10 ` Chris Wilson
@ 2012-04-11 22:37 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2012-04-11 22:37 UTC (permalink / raw)
To: Chris Wilson
Cc: Ben Widawsky, f, Daniel Vetter, intel-gfx, Ben Widawsky,
Arjan van de Ven
On Wed, Apr 11, 2012 at 11:10:05PM +0100, Chris Wilson wrote:
> On Wed, 11 Apr 2012 09:14:43 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > I'm down to just bikeshedding over useless lines of code which do not
> > even add visual clarity...
> >
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Oops, need to learn to spot 64-bit divides which become an issue on
> 32-bit builds.
Squashed onto Ben's patch and updated dinq pushed.
Thanks, Daniel
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 2319f06..f1b5108 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -35,14 +35,12 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> u64 raw_time; /* 32b value may overflow during fixed point math */
> - u32 residency;
>
> if (!intel_enable_rc6(dev))
> return 0;
>
> - raw_time = I915_READ(reg) * 128ULL;
> - residency = DIV_ROUND_CLOSEST(raw_time, 1000) / 100;
> - return residency;
> + raw_time = I915_READ(reg) * 128ULL + 500;
> + return do_div(raw_time, 100000);
> }
>
> static ssize_t
> --
> 1.7.9.5
>
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2012-04-11 22:36 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2012-04-11 4:17 [PATCH v4] drm/i915: rc6 in sysfs Ben Widawsky
2012-04-11 8:14 ` Chris Wilson
2012-04-11 9:51 ` Daniel Vetter
2012-04-11 22:10 ` Chris Wilson
2012-04-11 22:37 ` Daniel Vetter
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