[PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs

[PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs

[Chris Wilson]

Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d5aa2d2..b97112c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2845,11 +2845,14 @@ found:
 	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
 prepare: /* separate function? */
 	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
-	I915_WRITE(pll->fp0_reg, fp);
-	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
 
+	/* Wait for the clocks to stabilize before rewriting the regs */
+	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(pll->pll_reg);
 	udelay(150);
+
+	I915_WRITE(pll->fp0_reg, fp);
+	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
 	pll->on = false;
 	return pll;
 }
-- 
1.7.10

Re: [PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs

[Ben Widawsky]

On Wed,  2 May 2012 20:43:56 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reported-and-tested-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d5aa2d2..b97112c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2845,11 +2845,14 @@ found:
>  	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
>  prepare: /* separate function? */
>  	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
> -	I915_WRITE(pll->fp0_reg, fp);
> -	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  
> +	/* Wait for the clocks to stabilize before rewriting the regs */
> +	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  	POSTING_READ(pll->pll_reg);
>  	udelay(150);
> +
> +	I915_WRITE(pll->fp0_reg, fp);
> +	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  	pll->on = false;
>  	return pll;
>  }



-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs

[Chris Wilson]

On Wed, 2 May 2012 13:14:59 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> On Wed,  2 May 2012 20:43:56 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:

When initialising the PLL registers we may have to clear existing state
from the BIOS - that is the PLL may already be enabled. So we need to
disable it, wait for the clocks to settle and then rewrite it.

The issue came to light when Ben tested

commit 88ca4bb7974277793e602d88739d4e8f56b89e64
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Fri Apr 20 17:11:53 2012 +0100

    drm/i915: manage PCH PLLs separately from pipes

and found that booting into a VGA monitor was no longer working. Closer
inspection suggests that it was a pre-existing bug now being hit by the
rearranged code. Perhaps Ben was not even the first person to stumble
upon this bug, https://bugs.freedesktop.org/show_bug.cgi?id=37029.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ben Widawsky <ben@bwidawsk.net>
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Reported-and-tested-by: Ben Widawsky <ben@bwidawsk.net>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: Wait for the clocks to stabilise before updating PLLs

[Daniel Vetter]

On Wed, May 02, 2012 at 09:26:36PM +0100, Chris Wilson wrote:
> On Wed, 2 May 2012 13:14:59 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> > On Wed,  2 May 2012 20:43:56 +0100
> > Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> When initialising the PLL registers we may have to clear existing state
> from the BIOS - that is the PLL may already be enabled. So we need to
> disable it, wait for the clocks to settle and then rewrite it.
>
> The issue came to light when Ben tested
>
> commit 88ca4bb7974277793e602d88739d4e8f56b89e64
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date:   Fri Apr 20 17:11:53 2012 +0100
>
>     drm/i915: manage PCH PLLs separately from pipes
>
> and found that booting into a VGA monitor was no longer working. Closer
> inspection suggests that it was a pre-existing bug now being hit by the
> rearranged code. Perhaps Ben was not even the first person to stumble
> upon this bug, https://bugs.freedesktop.org/show_bug.cgi?id=37029.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Ben Widawsky <ben@bwidawsk.net>
> > > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Reported-and-tested-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48