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From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 07/17] Openrisc: add int instruction helpers
Date: Sun, 27 May 2012 13:32:49 +0800	[thread overview]
Message-ID: <1338096779-30821-8-git-send-email-proljc@gmail.com> (raw)
In-Reply-To: <1338096779-30821-1-git-send-email-proljc@gmail.com>

add int piont instruction helpers for openrisc.

Signed-off-by: Jia Liu <proljc@gmail.com>
---
 Makefile.target              |    2 +-
 target-openrisc/helper.h     |    8 +++
 target-openrisc/int_helper.c |  155 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 target-openrisc/int_helper.c

diff --git a/Makefile.target b/Makefile.target
index 42574f6..d68c168 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -101,7 +101,7 @@ endif
 libobj-$(TARGET_SPARC) += int32_helper.o
 libobj-$(TARGET_SPARC64) += int64_helper.o
 libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
-libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o \
+libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o int_helper.o\
 intrpt.o intrpt_helper.o mmu.o mmu_helper.o
 
 libobj-y += disas.o
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index fbcfd12..3d82d24 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -22,6 +22,14 @@
 /* exception */
 DEF_HELPER_FLAGS_2(exception, 0, void, env, i32)
 
+/* int */
+DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
+DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
+DEF_HELPER_FLAGS_3(add, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(addc, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(sub, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(mul, 0, tl, env, tl, tl)
+
 /* interrupt */
 DEF_HELPER_FLAGS_1(rfe, 0, void, env)
 
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
new file mode 100644
index 0000000..4e6b9ac
--- /dev/null
+++ b/target-openrisc/int_helper.c
@@ -0,0 +1,155 @@
+/*
+ *  Openrisc int helper routines
+ *
+ *  Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *                          Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+#include "excp.h"
+
+target_ulong HELPER(ff1)(target_ulong x)
+{
+    target_ulong n = 0;
+
+    if (x == 0) {
+        return 0;
+    }
+
+    for (n = 32; x; n--) {
+        x <<= 1;
+    }
+    return n+1;
+}
+
+target_ulong HELPER(fl1)(target_ulong x)
+{
+    target_ulong n = 0;
+
+    if (x == 0) {
+        return 0;
+    }
+
+    for (n = 0; x; n++) {
+        x >>= 1;
+    }
+    return n;
+}
+
+target_ulong HELPER(add)(CPUOpenriscState * env, target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    result = a + b;
+
+    if (result < a) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b ^ -1) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(addc)(CPUOpenriscState * env,
+                          target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    int cf = env->sr & SR_CY;
+
+    if (!cf) {
+        result = a + b;
+        cf = result < a;
+    } else {
+        result = a + b + 1;
+        cf = result <= a;
+    }
+
+    if (cf) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b ^ -1) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(sub)(CPUOpenriscState * env, target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    result = a - b;
+    if (a >= b) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(mul)(CPUOpenriscState * env, target_ulong a, target_ulong b)
+{
+    uint64_t result;
+    result = a * b;
+    target_ulong high;
+
+    high = result >> (sizeof(target_ulong) * 8);
+
+    if (((result >> ((sizeof(target_ulong) * 8) - 1)) & 0x1) == 0) {
+        if (high == 0) {
+            return result;
+        }
+    }
+
+    if (((result >> ((sizeof(target_ulong) * 8) - 1)) & 0x1) == 1) {
+        if (high == 0xffffffff) {
+            return result;
+        }
+    }
+
+    env->sr |= SR_OV;
+    env->sr |= SR_CY;
+
+    if (env->sr & SR_OVE) {
+        raise_exception(env, EXCP_RANGE);
+    }
+
+    return result;
+}
-- 
1.7.9.5

  parent reply	other threads:[~2012-05-27  5:35 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-05-27  5:32 [Qemu-devel] [PATCH v2 00/17] Qemu Openrisc support Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 01/17] Openrisc: add target stubs Jia Liu
2012-05-27 12:44   ` Andreas Färber
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 02/17] Openrisc: add cpu QOM implement Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 03/17] Openrisc: add basic machine Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 04/17] Openrisc: add MMU support Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 05/17] Openrisc: add interrupt support Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 06/17] Openrisc: add exception support Jia Liu
2012-05-27  5:32 ` Jia Liu [this message]
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 08/17] Openrisc: add float instruction helpers Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 09/17] Openrisc: add instruction translation routines Jia Liu
2012-05-28 11:38   ` Max Filippov
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Controller Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 11/17] Openrisc: add a timer Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 12/17] Openrisc: add a simulator board Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 13/17] Openrisc: add system instruction helpers Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 14/17] Openrisc: add gdb stub support Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 15/17] Openrisc: add linux syscall, signal and termbits Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 16/17] Openrisc: add linux user support Jia Liu
2012-05-27  5:32 ` [Qemu-devel] [PATCH v2 17/17] Openrisc: add testcases Jia Liu
2012-05-27  6:01 ` [Qemu-devel] [PATCH v2 00/17] Qemu Openrisc support Stefan Weil
2012-05-27  6:10   ` Jia Liu

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