From: Robert Richter <robert.richter@amd.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Robert Richter <robert.richter@amd.com>
Subject: [PATCH 00/10] perf, x86: Add northbridge counter support for AMD family 15h
Date: Tue, 19 Jun 2012 20:10:38 +0200 [thread overview]
Message-ID: <1340129448-8690-1-git-send-email-robert.richter@amd.com> (raw)
This patch adds northbridge counter support for AMD family 15h cpus.
The NB counter implementation and usage is in the same way as for
family 10h. Thus a nb event can now be selected as any other
performance counter event. As for family 10h the kernel selects only
one NB PMC per node by using the nb constraint handler.
Main part of this patch set is to rework current code in a way that
bit masks for counters can be used. Also, Intel's fixed counters have
been moved to Intel only code. This is since AMD nb counters start at
index 32 which leads to holes in the counter mask and causes conflicts
with fixed counters.
Another major change is the unification of AMD pmus and, where
possible, a family independent feature check based on cpuid.
It should also be mentioned that nb perfctrs do not support all bits
in the config value, see patch #10.
-Robert
Robert Richter (10):
perf, amd: Rework northbridge event constraints handler
perf, x86: Rework counter reservation code
perf, x86: Use bitmasks for generic counters
perf, x86: Rename Intel specific macros
perf, x86: Move Intel specific code to intel_pmu_init()
perf, amd: Unify AMD's generic and family 15h pmus
perf, amd: Generalize northbridge constraints code for family 15h
perf, amd: Enable northbridge counters on family 15h
perf, x86: Improve debug output in check_hw_exists()
perf, amd: Check northbridge event config value
arch/x86/include/asm/cpufeature.h | 2 +
arch/x86/include/asm/kvm_host.h | 4 +-
arch/x86/include/asm/perf_event.h | 26 ++-
arch/x86/kernel/cpu/perf_event.c | 129 +++++------
arch/x86/kernel/cpu/perf_event.h | 7 +
arch/x86/kernel/cpu/perf_event_amd.c | 368 +++++++++++++++++------------
arch/x86/kernel/cpu/perf_event_intel.c | 65 +++++-
arch/x86/kernel/cpu/perf_event_intel_ds.c | 4 +-
arch/x86/kernel/cpu/perf_event_p4.c | 8 +-
arch/x86/kvm/pmu.c | 22 +-
arch/x86/oprofile/op_model_amd.c | 4 +-
11 files changed, 374 insertions(+), 265 deletions(-)
--
1.7.8.4
next reply other threads:[~2012-06-19 18:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-19 18:10 Robert Richter [this message]
2012-06-19 18:10 ` [PATCH 01/10] perf, amd: Rework northbridge event constraints handler Robert Richter
2012-06-19 18:10 ` [PATCH 02/10] perf, x86: Rework counter reservation code Robert Richter
2012-06-19 18:10 ` [PATCH 03/10] perf, x86: Use bitmasks for generic counters Robert Richter
2012-06-19 18:10 ` [PATCH 04/10] perf, x86: Rename Intel specific macros Robert Richter
2012-06-19 18:10 ` [PATCH 05/10] perf, x86: Move Intel specific code to intel_pmu_init() Robert Richter
2012-06-20 9:36 ` Peter Zijlstra
2012-06-20 14:22 ` Robert Richter
2012-06-19 18:10 ` [PATCH 06/10] perf, amd: Unify AMD's generic and family 15h pmus Robert Richter
2012-06-19 18:10 ` [PATCH 07/10] perf, amd: Generalize northbridge constraints code for family 15h Robert Richter
2012-06-19 18:10 ` [PATCH 08/10] perf, amd: Enable northbridge counters on " Robert Richter
2012-06-19 18:10 ` [PATCH 09/10] perf, x86: Improve debug output in check_hw_exists() Robert Richter
2012-06-19 18:10 ` [PATCH 10/10] perf, amd: Check northbridge event config value Robert Richter
2012-06-20 8:36 ` [PATCH 00/10] perf, x86: Add northbridge counter support for AMD family 15h Stephane Eranian
2012-06-20 8:54 ` Peter Zijlstra
[not found] ` <CABPqkBS9hRxKLsecVK+AgRue6oqTtAg4=0Dpd5Z2VwAUja50fw@mail.gmail.com>
2012-06-20 9:29 ` Robert Richter
2012-06-20 9:38 ` Peter Zijlstra
2012-06-20 10:00 ` Robert Richter
2012-06-20 10:16 ` Peter Zijlstra
2012-06-20 12:29 ` Robert Richter
2012-06-20 15:54 ` Peter Zijlstra
2012-06-20 16:08 ` Peter Zijlstra
2012-06-20 16:21 ` Stephane Eranian
2012-06-20 10:46 ` Stephane Eranian
2012-06-20 12:41 ` Robert Richter
2012-06-20 9:41 ` Peter Zijlstra
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