From: Dave Airlie <airlied@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 1/3] pci_regs: define LNKSTA2 pcie cap + bits.
Date: Wed, 27 Jun 2012 08:35:52 +0100 [thread overview]
Message-ID: <1340782554-9865-1-git-send-email-airlied@gmail.com> (raw)
From: Dave Airlie <airlied@redhat.com>
We need these for detecting the max link speed for drm drivers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
include/linux/pci_regs.h | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 4b608f5..7f04132 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -521,6 +521,11 @@
#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
+#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
+#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
+#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
+#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
--
1.7.7.6
next reply other threads:[~2012-06-27 7:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-27 7:35 Dave Airlie [this message]
2012-06-27 7:35 ` [PATCH 2/3] drm/pci: add support for getting the supported link bw Dave Airlie
2012-06-27 7:35 ` [PATCH 3/3] drm/radeon/kms: auto detect pcie link speed from root port Dave Airlie
2012-06-28 9:45 ` [PATCH 1/3] pci_regs: define LNKSTA2 pcie cap + bits Dave Airlie
2012-07-02 20:01 ` Bjorn Helgaas
2012-06-28 13:10 ` Alex Deucher
2012-06-29 6:50 ` Boszormenyi Zoltan
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