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From: Boszormenyi Zoltan <zboszor@pr.hu>
To: Dave Airlie <airlied@gmail.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/3] pci_regs: define LNKSTA2 pcie cap + bits.
Date: Fri, 29 Jun 2012 08:50:11 +0200	[thread overview]
Message-ID: <4FED5023.5090805@pr.hu> (raw)
In-Reply-To: <1340782554-9865-1-git-send-email-airlied@gmail.com>

Hi,

2012-06-27 09:35 keltezéssel, Dave Airlie írta:
> From: Dave Airlie <airlied@redhat.com>
>
> We need these for detecting the max link speed for drm drivers.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>

I have reported this in March:
http://lists.freedesktop.org/archives/dri-devel/2012-March/019731.html

Since then, this motherboard received 3 BIOS upgrades (latest is
version 1208) and the system was upgraded to Fedora 17.

With kernel 3.5-rc4+ (commit 47b514cd476db2eca066a2ad31501b079d6c9cce)
plus this series of patches, the reported problem doesn't appear anymore.

lspci reports PCIe gen2 speed for my Radeon HD6570 and
gen1 speed for my 3ware 9650SE:

[zozo@localhost ~]$ sudo lspci -vvv -s 01:00.0
01:00.0 VGA compatible controller: ATI Technologies Inc NI Turks [AMD Radeon HD 6500] 
(prog-if 00 [VGA controller])
     Subsystem: PC Partner Limited Device e193
     Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- 
FastB2B- DisINTx+
     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- 
 >SERR- <PERR- INTx-
     Latency: 0, Cache Line Size: 64 bytes
     Interrupt: pin A routed to IRQ 88
     Region 0: Memory at c0000000 (64-bit, prefetchable) [size=256M]
     Region 2: Memory at fea20000 (64-bit, non-prefetchable) [size=128K]
     Region 4: I/O ports at e000 [size=256]
     Expansion ROM at fea00000 [disabled] [size=128K]
     Capabilities: [50] Power Management version 3
         Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
         Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
     Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00
         DevCap:    MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
             ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
             MaxPayload 128 bytes, MaxReadReq 512 bytes
         DevSta:    CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
         LnkCap:    Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us
             ClockPM- Surprise- LLActRep- BwNot-
         LnkCtl:    ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
             ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
         LnkSta:    Speed 5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
         DevCap2: Completion Timeout: Not Supported, TimeoutDis-
         DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
         LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable 
De-emphasis: -6dB
              Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
              Compliance De-emphasis: -6dB
         LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, 
EqualizationPhase1-
              EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
     Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
         Address: 00000000feeff00c  Data: 419a
     Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
     Capabilities: [150 v1] Advanced Error Reporting
         UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- 
UnsupReq- ACSViol-
         UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- 
UnsupReq- ACSViol-
         UESvrt:    DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ 
ECRC- UnsupReq- ACSViol-
         CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
         CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
         AERCap:    First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
     Kernel driver in use: radeon

[zozo@localhost ~]$ sudo lspci -vvv -s 08:00.0
08:00.0 RAID bus controller: 3ware Inc 9650SE SATA-II RAID PCIe (rev 01)
     Subsystem: 3ware Inc 9650SE SATA-II RAID PCIe
     Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- 
FastB2B- DisINTx-
     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- 
 >SERR- <PERR- INTx-
     Latency: 0, Cache Line Size: 64 bytes
     Interrupt: pin A routed to IRQ 16
     Region 0: Memory at d0000000 (64-bit, prefetchable) [size=32M]
     Region 2: Memory at fe420000 (64-bit, non-prefetchable) [size=4K]
     Region 4: I/O ports at 9000 [size=256]
     Expansion ROM at fe400000 [disabled] [size=128K]
     Capabilities: [40] Power Management version 2
         Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
         Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
     Capabilities: [50] MSI: Enable- Count=1/32 Maskable- 64bit+
         Address: 0000000000000000  Data: 0000
     Capabilities: [70] Express (v1) Legacy Endpoint, MSI 00
         DevCap:    MaxPayload 512 bytes, PhantFunc 0, Latency L0s <128ns, L1 <2us
             ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
             MaxPayload 128 bytes, MaxReadReq 512 bytes
         DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
         LnkCap:    Port #0, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <512ns, L1 <64us
             ClockPM- Surprise- LLActRep+ BwNot-
         LnkCtl:    ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk-
             ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
         LnkSta:    Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt-
     Capabilities: [100 v1] Advanced Error Reporting
         UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- 
UnsupReq- ACSViol-
         UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- 
UnsupReq- ACSViol-
         UESvrt:    DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ 
ECRC- UnsupReq- ACSViol-
         CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
         CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
         AERCap:    First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
     Kernel driver in use: 3w-9xxx

You can take this report as:

Tested-by: Zoltán Böszörményi <zboszor@pr.hu>

> ---
>   include/linux/pci_regs.h |    5 +++++
>   1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
> index 4b608f5..7f04132 100644
> --- a/include/linux/pci_regs.h
> +++ b/include/linux/pci_regs.h
> @@ -521,6 +521,11 @@
>   #define  PCI_EXP_OBFF_MSGA_EN	0x2000	/* OBFF enable with Message type A */
>   #define  PCI_EXP_OBFF_MSGB_EN	0x4000	/* OBFF enable with Message type B */
>   #define  PCI_EXP_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */
> +#define PCI_EXP_LNKCAP2		44	/* Link Capability 2 */
> +#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x01	/* Current Link Speed 2.5GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x02	/* Current Link Speed 5.0GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04	/* Current Link Speed 8.0GT/s */
> +#define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
>   #define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
>   #define PCI_EXP_SLTCTL2		56	/* Slot Control 2 */
>   

      parent reply	other threads:[~2012-06-29  7:08 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-27  7:35 [PATCH 1/3] pci_regs: define LNKSTA2 pcie cap + bits Dave Airlie
2012-06-27  7:35 ` [PATCH 2/3] drm/pci: add support for getting the supported link bw Dave Airlie
2012-06-27  7:35 ` [PATCH 3/3] drm/radeon/kms: auto detect pcie link speed from root port Dave Airlie
2012-06-28  9:45 ` [PATCH 1/3] pci_regs: define LNKSTA2 pcie cap + bits Dave Airlie
2012-07-02 20:01   ` Bjorn Helgaas
2012-06-28 13:10 ` Alex Deucher
2012-06-29  6:50 ` Boszormenyi Zoltan [this message]

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