* [PATCH ddx] Add Haswell PCI IDs
@ 2012-08-06 21:48 Paulo Zanoni
2012-08-06 22:20 ` Rodrigo Vivi
2012-08-07 14:28 ` Guo, Chaohong
0 siblings, 2 replies; 4+ messages in thread
From: Paulo Zanoni @ 2012-08-06 21:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
src/intel_driver.h | 37 +++++++++++++++++++++++++++
src/intel_module.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 110 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 882d889..ac02cc7 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -192,6 +192,43 @@
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
+#define PCI_CHIP_HASWELL_D_GT1 0x0402
+#define PCI_CHIP_HASWELL_D_GT2 0x0412
+#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
+#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
+#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+
#endif
#define I85X_CAPID 0x44
diff --git a/src/intel_module.c b/src/intel_module.c
index ae19f75..c0403ca 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
{PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
{PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
+ {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
+ {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" },
{-1, NULL}
};
#define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0]))
@@ -221,6 +257,43 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
+
INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
{ 0, 0, 0 },
};
--
1.7.11.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH ddx] Add Haswell PCI IDs
2012-08-06 21:48 [PATCH ddx] Add Haswell PCI IDs Paulo Zanoni
@ 2012-08-06 22:20 ` Rodrigo Vivi
2012-08-07 10:41 ` Chris Wilson
2012-08-07 14:28 ` Guo, Chaohong
1 sibling, 1 reply; 4+ messages in thread
From: Rodrigo Vivi @ 2012-08-06 22:20 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Mon, Aug 6, 2012 at 6:48 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> src/intel_driver.h | 37 +++++++++++++++++++++++++++
> src/intel_module.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 110 insertions(+)
>
> diff --git a/src/intel_driver.h b/src/intel_driver.h
> index 882d889..ac02cc7 100644
> --- a/src/intel_driver.h
> +++ b/src/intel_driver.h
> @@ -192,6 +192,43 @@
> #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
> #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
>
> +#define PCI_CHIP_HASWELL_D_GT1 0x0402
> +#define PCI_CHIP_HASWELL_D_GT2 0x0412
> +#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
> +#define PCI_CHIP_HASWELL_M_GT1 0x0406
> +#define PCI_CHIP_HASWELL_M_GT2 0x0416
> +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
> +#define PCI_CHIP_HASWELL_S_GT1 0x040A
> +#define PCI_CHIP_HASWELL_S_GT2 0x041A
> +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
> +#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
> +#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
> +#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
> +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
> +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
> +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
> +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
> +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
> +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
> +#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
> +#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
> +#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
> +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
> +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
> +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
> +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
> +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
> +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
> +#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
> +#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
> +#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
> +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
> +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
> +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
> +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
> +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
> +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
> +
> #endif
>
> #define I85X_CAPID 0x44
> diff --git a/src/intel_module.c b/src/intel_module.c
> index ae19f75..c0403ca 100644
> --- a/src/intel_module.c
> +++ b/src/intel_module.c
> @@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = {
> {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
> {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
> {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
> + {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
> + {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
> + {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" },
> + {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
> + {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
> + {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" },
> + {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
> + {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
> + {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" },
> + {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
> + {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
> + {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" },
> + {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" },
> + {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" },
> + {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" },
> + {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
> + {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
> + {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" },
> + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
> + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
> + {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" },
> + {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
> + {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
> + {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" },
> + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
> + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
> + {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" },
> + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
> + {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
> + {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" },
> + {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
> + {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
> + {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" },
> + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
> + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
> + {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" },
> {-1, NULL}
> };
> #define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0]))
> @@ -221,6 +257,43 @@ static const struct pci_id_match intel_device_match[] = {
> INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
> INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
>
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
> + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
> +
> INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
> { 0, 0, 0 },
> };
> --
> 1.7.11.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH ddx] Add Haswell PCI IDs
2012-08-06 22:20 ` Rodrigo Vivi
@ 2012-08-07 10:41 ` Chris Wilson
0 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2012-08-07 10:41 UTC (permalink / raw)
To: Rodrigo Vivi, Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Mon, 6 Aug 2012 19:20:29 -0300, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Thanks for the patch and the careful review, pushed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH ddx] Add Haswell PCI IDs
2012-08-06 21:48 [PATCH ddx] Add Haswell PCI IDs Paulo Zanoni
2012-08-06 22:20 ` Rodrigo Vivi
@ 2012-08-07 14:28 ` Guo, Chaohong
1 sibling, 0 replies; 4+ messages in thread
From: Guo, Chaohong @ 2012-08-07 14:28 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx@lists.freedesktop.org, Zanoni, Paulo R
Why using "xxx_SDV_xxx" in the macros ? Is there an official
Name for those chips ? Besides, what does "CRW" stands
For ?
Thanks,
-minskey
-----Original Message-----
From: intel-gfx-bounces+chaohong.guo=intel.com@lists.freedesktop.org [mailto:intel-gfx-bounces+chaohong.guo=intel.com@lists.freedesktop.org] On Behalf Of Paulo Zanoni
Sent: Tuesday, August 07, 2012 5:48 AM
To: intel-gfx@lists.freedesktop.org
Cc: Zanoni, Paulo R
Subject: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
src/intel_driver.h | 37 +++++++++++++++++++++++++++ src/intel_module.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 110 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h index 882d889..ac02cc7 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -192,6 +192,43 @@
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
+#define PCI_CHIP_HASWELL_D_GT1 0x0402
+#define PCI_CHIP_HASWELL_D_GT2 0x0412
+#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
+#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
+#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+
#endif
#define I85X_CAPID 0x44
diff --git a/src/intel_module.c b/src/intel_module.c index ae19f75..c0403ca 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
{PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
{PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
+ {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
+ {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" },
{-1, NULL}
};
#define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0])) @@ -221,6 +257,43 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS,
+&intel_haswell_info ),
+
INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
{ 0, 0, 0 },
};
--
1.7.11.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-08-07 14:28 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-08-06 21:48 [PATCH ddx] Add Haswell PCI IDs Paulo Zanoni
2012-08-06 22:20 ` Rodrigo Vivi
2012-08-07 10:41 ` Chris Wilson
2012-08-07 14:28 ` Guo, Chaohong
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.