[PATCH] drm/i915: Fix gem_gtt_cpu_tlb

[PATCH] drm/i915: Fix gem_gtt_cpu_tlb

[Ben Widawsky]

Revert "agp/intel, drm/i915: Use a write-combining map for updating PTEs"

This reverts commit 15a80851c8166c05c6f600fede1719b29eb70737.

I haven't spent any time looking at the patch but bisection and revert
testing proves this fixes the issues. Begone ye ext4 errors!

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/char/agp/intel-gtt.c    | 13 +++----------
 drivers/gpu/drm/i915/i915_dma.c | 14 ++------------
 2 files changed, 5 insertions(+), 22 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index be506ac..9ed92ef 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -674,14 +674,8 @@ static int intel_gtt_init(void)
 
 	gtt_map_size = intel_private.base.gtt_total_entries * 4;
 
-	intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
-				       gtt_map_size);
-	if (!intel_private.gtt) {
-		dev_err(&intel_private.bridge_dev->dev,
-			"failed to map GATT as wc, falling back to uc-\n");
-		intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
-					    gtt_map_size);
-	}
+	intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
+				    gtt_map_size);
 	if (!intel_private.gtt) {
 		intel_private.driver->cleanup();
 		iounmap(intel_private.registers);
@@ -1234,13 +1228,12 @@ static inline int needs_idle_maps(void)
 static int i9xx_setup(void)
 {
 	u32 reg_addr;
-	int size;
+	int size = KB(512);
 
 	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
 
 	reg_addr &= 0xfff80000;
 
-	size = KB(512);
 	if (INTEL_GTT_GEN >= 7)
 		size = MB(2);
 
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c81375c..2285ae3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1458,7 +1458,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
 	struct drm_i915_private *dev_priv;
 	struct intel_device_info *info;
-	int ret = 0, mmio_bar, mmio_size;
+	int ret = 0, mmio_bar;
 	uint32_t aperture_size;
 
 	info = (struct intel_device_info *) flags;
@@ -1522,18 +1522,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 
-	/* Restrict iomap to avoid clobbering the GTT which we want WC mapped.
-	 * Do not attempt to map the whole BAR!
-	 */
 	mmio_bar = IS_GEN2(dev) ? 1 : 0;
-	if (info->gen < 3)
-		mmio_size = 64*1024;
-	else if (info->gen < 5)
-		mmio_size = 512*1024;
-	else
-		mmio_size = 2*1024*1024;
-
-	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
+	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
 	if (!dev_priv->regs) {
 		DRM_ERROR("failed to map registers\n");
 		ret = -EIO;
-- 
1.7.11.5

Re: [PATCH] drm/i915: Fix gem_gtt_cpu_tlb

[Daniel Vetter]

On Thu, Aug 16, 2012 at 11:12:57PM -0700, Ben Widawsky wrote:
> Revert "agp/intel, drm/i915: Use a write-combining map for updating PTEs"
> 
> This reverts commit 15a80851c8166c05c6f600fede1719b29eb70737.
> 
> I haven't spent any time looking at the patch but bisection and revert
> testing proves this fixes the issues. Begone ye ext4 errors!
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Patched removed from dinq, thanks a lot to you (and Paulo) for digging
this out.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH] drm/i915: Fix gem_gtt_cpu_tlb

[Chris Wilson]

On Fri, 17 Aug 2012 10:13:34 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Aug 16, 2012 at 11:12:57PM -0700, Ben Widawsky wrote:
> > Revert "agp/intel, drm/i915: Use a write-combining map for updating PTEs"
> > 
> > This reverts commit 15a80851c8166c05c6f600fede1719b29eb70737.
> > 
> > I haven't spent any time looking at the patch but bisection and revert
> > testing proves this fixes the issues. Begone ye ext4 errors!
> > 
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Patched removed from dinq, thanks a lot to you (and Paulo) for digging
> this out.

The regression appears to have been introduced with SNB. Maybe we should
bug the hw engineers about this?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre