* [U-Boot] reg: P2020 include config file - u-boot basic doubt
@ 2012-10-16 12:51 vidya Krishnamoorthy
2012-10-16 17:52 ` Scott Wood
0 siblings, 1 reply; 2+ messages in thread
From: vidya Krishnamoorthy @ 2012-10-16 12:51 UTC (permalink / raw)
To: u-boot
Hi
Anybody worked in P2020 ..Please clarify my basic doubt
The e500 core datasheet says processor reset vector address is 0xFFFFFFC
but in p2020 u-boot config file , CONFIG_RESET_VECTOR_ADDRESS is
defined as 0xEFFFFFFC.
With boot sequencer disabled and with BPTR reg value = 0, how the
reset vector address will change from 0xfffffffC to effffffC in u-boot
Please help me to understand
^ permalink raw reply [flat|nested] 2+ messages in thread
* [U-Boot] reg: P2020 include config file - u-boot basic doubt
2012-10-16 12:51 [U-Boot] reg: P2020 include config file - u-boot basic doubt vidya Krishnamoorthy
@ 2012-10-16 17:52 ` Scott Wood
0 siblings, 0 replies; 2+ messages in thread
From: Scott Wood @ 2012-10-16 17:52 UTC (permalink / raw)
To: u-boot
On 10/16/2012 07:51:24 AM, vidya Krishnamoorthy wrote:
> Hi
>
> Anybody worked in P2020 ..Please clarify my basic doubt
>
> The e500 core datasheet says processor reset vector address is
> 0xFFFFFFC
>
> but in p2020 u-boot config file , CONFIG_RESET_VECTOR_ADDRESS is
> defined as 0xEFFFFFFC.
>
> With boot sequencer disabled and with BPTR reg value = 0, how the
> reset vector address will change from 0xfffffffC to effffffC in
> u-boot
0xfffffffc is the reset vector at power-on, and is where the upper 8
MiB of NOR flash is mapped immediately after reset. 0xeffffffc is the
link address of the branch instruction that goes at the reset vector,
after software changes the mapping of NOR flash to its permanent
location.
-Scott
^ permalink raw reply [flat|nested] 2+ messages in thread
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2012-10-16 12:51 [U-Boot] reg: P2020 include config file - u-boot basic doubt vidya Krishnamoorthy
2012-10-16 17:52 ` Scott Wood
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