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* [PATCH 1/3] ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode
@ 2012-10-24  8:54 Bastian Hecht
  0 siblings, 0 replies; 3+ messages in thread
From: Bastian Hecht @ 2012-10-24  8:54 UTC (permalink / raw)
  To: linux-sh

We can remove the extra code of modify_scu_cpu_psr() and use the cleaner
generic ARM helper scu_power_mode(). As every CPU only deals with its
own power register and scu_power_mode() operates with 8-bit accesses,
we save the locking overhead too.

Signed-off-by: Bastian Hecht <hechtb@gmail.com>
---
 arch/arm/mach-shmobile/smp-emev2.c |   22 ++--------------------
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f674562..535426c 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,24 +32,8 @@
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
 static void __iomem *scu_base;
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-	unsigned long tmp;
-
-	/* we assume this code is running on a different cpu
-	 * than the one that is changing coherency setting */
-	spin_lock(&scu_lock);
-	tmp = readl(scu_base + 8);
-	tmp &= ~clr;
-	tmp |= set;
-	writel(tmp, scu_base + 8);
-	spin_unlock(&scu_lock);
-
-}
-
 static unsigned int __init emev2_get_core_count(void)
 {
 	if (!scu_base) {
@@ -95,7 +79,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
 	cpu = cpu_logical_map(cpu);
 
 	/* enable cache coherency */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
+	scu_power_mode(scu_base, 0);
 
 	/* Tell ROM loader about our vector (in headsmp.S) */
 	emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -106,12 +90,10 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-	int cpu = cpu_logical_map(0);
-
 	scu_enable(scu_base);
 
 	/* enable cache coherency on CPU0 */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
+	scu_power_mode(scu_base, 0);
 }
 
 static void __init emev2_smp_init_cpus(void)
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [PATCH 0/3] Use generic helper scu_power_mode()
@ 2012-10-25 10:58 Bastian Hecht
  2012-10-25 10:58   ` Bastian Hecht
  0 siblings, 1 reply; 3+ messages in thread
From: Bastian Hecht @ 2012-10-25 10:58 UTC (permalink / raw)
  To: linux-arm-kernel

Reposted to include the arch/arm mailing list.

The shmobile series implements its own code for setting the SCU power
register of the ARM MPCore. It uses 32-bit wide access and thus needs
locking as multiple CPUs might access it simultaneously for change. There is
already a small helper function that avoids the overhead by using 8-bit
wide access: As every CPU only accesses its own field we can drop the
lock and use it.

Bastian Hecht (3):
  ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode
  ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode
  ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with
    scu_power_mode

 arch/arm/mach-shmobile/smp-emev2.c   |   22 ++--------------------
 arch/arm/mach-shmobile/smp-r8a7779.c |   25 +++----------------------
 arch/arm/mach-shmobile/smp-sh73a0.c  |   23 ++---------------------
 3 files changed, 7 insertions(+), 63 deletions(-)

-- 
1.7.9.5


^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-10-25 10:58 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2012-10-24  8:54 [PATCH 1/3] ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode Bastian Hecht
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2012-10-25 10:58 [PATCH 0/3] Use generic helper scu_power_mode() Bastian Hecht
2012-10-25 10:58 ` [PATCH 1/3] ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode Bastian Hecht
2012-10-25 10:58   ` Bastian Hecht

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