From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 06/10] drm/i915: don't intel_crt_init if DDI A has 4 lanes
Date: Tue, 20 Nov 2012 13:27:40 -0200 [thread overview]
Message-ID: <1353425264-3728-7-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
DDI A and E have 4 lanes to share, so if DDI A is using 4 lanes,
there's nothing left for DDI E, which means there's no CRT port on the
machine.
The bit we're checking here is programmed at system boot and it cannot
be changed afterwards, so we cannot change the amount of lanes
reserved for each DDI port.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d83876..5aba146 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4515,6 +4515,7 @@
#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
#define DDI_BUF_EMP_MASK (0xf<<24)
#define DDI_BUF_IS_IDLE (1<<7)
+#define DDI_A_4_LANES (1<<4)
#define DDI_PORT_WIDTH_X1 (0<<1)
#define DDI_PORT_WIDTH_X2 (1<<1)
#define DDI_PORT_WIDTH_X4 (3<<1)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e4d7079..dd7aafc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8258,7 +8258,9 @@ static void intel_setup_outputs(struct drm_device *dev)
I915_WRITE(PFIT_CONTROL, 0);
}
- intel_crt_init(dev);
+ if (!(IS_HASWELL(dev) &&
+ (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
+ intel_crt_init(dev);
if (IS_HASWELL(dev)) {
int found;
--
1.7.11.7
next prev parent reply other threads:[~2012-11-20 15:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-20 15:27 [PATCH 00/10] Random Haswell fixes Paulo Zanoni
2012-11-20 15:27 ` [PATCH 01/10] drm/i915: don't limit Haswell CRT encoder to pipe A Paulo Zanoni
2012-11-20 18:20 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 02/10] drm/i915: fix FDI lane calculation Paulo Zanoni
2012-11-20 18:17 ` Damien Lespiau
2012-11-20 18:43 ` Paulo Zanoni
2012-11-20 15:27 ` [PATCH 03/10] drm/i915: use cpu/pch transcoder on intel_enable_pipe Paulo Zanoni
2012-11-20 18:23 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages Paulo Zanoni
2012-11-20 18:46 ` Damien Lespiau
2012-11-20 19:10 ` Paulo Zanoni
2012-11-20 19:24 ` Damien Lespiau
2012-11-20 19:34 ` Paulo Zanoni
2012-11-20 15:27 ` [PATCH 05/10] drm/i915: make DP work on LPT-LP machines Paulo Zanoni
2012-11-20 16:50 ` Daniel Vetter
2012-11-20 17:12 ` Paulo Zanoni
2012-11-20 19:00 ` Damien Lespiau
2012-11-20 19:14 ` Paulo Zanoni
2012-11-20 15:27 ` Paulo Zanoni [this message]
2012-11-20 19:12 ` [PATCH 06/10] drm/i915: don't intel_crt_init if DDI A has 4 lanes Damien Lespiau
2012-11-20 15:27 ` [PATCH 07/10] drm/i915: make the panel fitter work on pipes B and C on IVB Paulo Zanoni
2012-11-20 19:34 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 08/10] drm/i915: make the panel fitter work on pipes B and C on Haswell Paulo Zanoni
2012-11-20 19:35 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 09/10] drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines Paulo Zanoni
2012-11-20 19:59 ` Damien Lespiau
2012-11-20 15:27 ` [PATCH 10/10] drm/i915: implement WaMbcDriverBootEnable on Haswell Paulo Zanoni
2012-11-21 13:31 ` Daniel Vetter
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