From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 2/3] target-i386: enable PCLMULQDQ on Westmere CPU
Date: Thu, 28 Mar 2013 01:00:10 +0100 [thread overview]
Message-ID: <1364428811-8226-3-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1364428811-8226-1-git-send-email-aurelien@aurel32.net>
The PCLMULQDQ instruction has been introduced on the Westmere CPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 41382c5..5941d40 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = {
CPUID_DE | CPUID_FP87,
.ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_SSE3,
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
--
1.7.10.4
next prev parent reply other threads:[~2013-03-28 0:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-28 0:00 [Qemu-devel] [PATCH 0/3] target-i386: add PCLMULQDQ and AES-NI instructions Aurelien Jarno
2013-03-28 0:00 ` [Qemu-devel] [PATCH 1/3] target-i386: add pclmulqdq instruction Aurelien Jarno
2013-03-28 15:45 ` Richard Henderson
2013-03-28 0:00 ` Aurelien Jarno [this message]
2013-03-28 15:47 ` [Qemu-devel] [PATCH 2/3] target-i386: enable PCLMULQDQ on Westmere CPU Richard Henderson
2013-03-28 0:00 ` [Qemu-devel] [PATCH 3/3] target-i386: add AES-NI instructions Aurelien Jarno
2013-03-28 15:49 ` Richard Henderson
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