Re: [PATCH] drm/i915: hw state readout support for pipe_config->fdi_lanes

From: Imre Deak <imre.deak@intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: hw state readout support for pipe_config->fdi_lanes
Date: Mon, 29 Apr 2013 13:22:27 +0300	[thread overview]
Message-ID: <1367230947.6390.48.camel@intelbox> (raw)
In-Reply-To: <1366810228-28778-1-git-send-email-daniel.vetter@ffwll.ch>

On Wed, 2013-04-24 at 15:30 +0200, Daniel Vetter wrote:
> v2: Introduce some nice #defines for the FDI lane width fields and put
> them to good use. Suggested by Ville.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 11 +++--------
>  drivers/gpu/drm/i915/intel_ddi.c     |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 38 ++++++++++++++++++++++++++----------
>  3 files changed, 32 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 894d729..e96ee12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4138,10 +4138,9 @@
>  #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
>  #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
>  #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
> -#define  FDI_DP_PORT_WIDTH_X1           (0<<19)
> -#define  FDI_DP_PORT_WIDTH_X2           (1<<19)
> -#define  FDI_DP_PORT_WIDTH_X3           (2<<19)
> -#define  FDI_DP_PORT_WIDTH_X4           (3<<19)
> +#define  FDI_DP_PORT_WIDTH_SHIFT		19
> +#define  FDI_DP_PORT_WIDTH_MASK			(7 << 19)
> +#define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << 19)

You could use FDI_DP_PORT_WIDTH_SHIFT in the above two macros.

>  #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
>  /* Ironlake: hardwired to 1 */
>  #define  FDI_TX_PLL_ENABLE              (1<<14)
> @@ -4166,7 +4165,6 @@
>  /* train, dp width same as FDI_TX */
>  #define  FDI_FS_ERRC_ENABLE		(1<<27)
>  #define  FDI_FE_ERRC_ENABLE		(1<<26)
> -#define  FDI_DP_PORT_WIDTH_X8           (7<<19)
>  #define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
>  #define  FDI_8BPC                       (0<<16)
>  #define  FDI_10BPC                      (1<<16)
> @@ -4188,9 +4186,6 @@
>  #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
>  #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
>  #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
> -/* LPT */
> -#define  FDI_PORT_WIDTH_2X_LPT			(1<<19)
> -#define  FDI_PORT_WIDTH_1X_LPT			(0<<19)
>  
>  #define _FDI_RXA_MISC			0xf0010
>  #define _FDI_RXB_MISC			0xf1010
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1ecb0f3..96354a5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -182,7 +182,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	/* Enable the PCH Receiver FDI PLL */
>  	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
>  		     FDI_RX_PLL_ENABLE |
> -		     ((intel_crtc->config.fdi_lanes - 1) << 19);
> +		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
>  	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>  	POSTING_READ(_FDI_RXA_CTL);
>  	udelay(220);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 652c6b8..85ccd2d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2419,8 +2419,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
>  	/* enable CPU FDI TX and PCH FDI RX */
>  	reg = FDI_TX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	temp &= ~(7 << 19);
> -	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
> +	temp &= ~FDI_DP_PORT_WIDTH_SHIFT;

FDI_DP_PORT_WIDTH_MASK

> +	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
>  	temp &= ~FDI_LINK_TRAIN_NONE;
>  	temp |= FDI_LINK_TRAIN_PATTERN_1;
>  	I915_WRITE(reg, temp | FDI_TX_ENABLE);
> @@ -2517,8 +2517,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>  	/* enable CPU FDI TX and PCH FDI RX */
>  	reg = FDI_TX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	temp &= ~(7 << 19);
> -	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
> +	temp &= ~FDI_DP_PORT_WIDTH_MASK;
> +	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
>  	temp &= ~FDI_LINK_TRAIN_NONE;
>  	temp |= FDI_LINK_TRAIN_PATTERN_1;
>  	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> @@ -2652,8 +2652,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
>  	/* enable CPU FDI TX and PCH FDI RX */
>  	reg = FDI_TX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	temp &= ~(7 << 19);
> -	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
> +	temp &= ~FDI_DP_PORT_WIDTH_MASK;
> +	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
>  	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
>  	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
>  	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> @@ -2754,8 +2754,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>  	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
>  	reg = FDI_RX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	temp &= ~((0x7 << 19) | (0x7 << 16));
> -	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
> +	temp &= ~(FDI_DP_PORT_WIDTH_SHIFT | (0x7 << 16));

FDI_DP_PORT_WIDTH_MASK

Other than the above typos:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
>  	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
>  	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>  
> @@ -5763,9 +5763,14 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> -	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
> +	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		pipe_config->has_pch_encoder = true;
>  
> +		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
> +		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> +					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> +	}
> +
>  	return true;
>  }
>  
> @@ -5902,9 +5907,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	 */
>  	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>  	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
> -	    I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
> +	    I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
>  		pipe_config->has_pch_encoder = true;
>  
> +		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> +		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> +					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> +	}
> +
>  	return true;
>  }
>  
> @@ -7866,6 +7876,14 @@ intel_pipe_config_compare(struct intel_crtc_config *current_config,
>  		return false;
>  	}
>  
> +	if (current_config->fdi_lanes != pipe_config->fdi_lanes) {
> +		DRM_ERROR("mismatch in fdi_lanes "
> +			  "(expected %i, found %i)\n",
> +			  current_config->fdi_lanes,
> +			  pipe_config->fdi_lanes);
> +		return false;
> +	}
> +
>  	return true;
>  }
>  

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