From: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH 18/23] iommu/tegra: smmu: Workaround PCIe IOMMU'able
Date: Wed, 26 Jun 2013 12:28:21 +0300 [thread overview]
Message-ID: <1372238906-9346-19-git-send-email-hdoyu@nvidia.com> (raw)
Make PCIe work as it is. IOMMU support can be implemented later.
Signed-off-by: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/iommu/tegra-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 64da08a..6e82df3 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -402,6 +402,9 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,
for_each_set_bit(i, (unsigned long *)&map,
sizeof(map) * BITS_PER_BYTE) {
+ if (i == SWGID_AFI) /* FIXME: IOMMU'able PCIe */
+ continue;
+
offs = HWGRP_ASID_REG(i);
val = smmu_read(smmu, offs);
if (on) {
--
1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: hdoyu@nvidia.com (Hiroshi Doyu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 18/23] iommu/tegra: smmu: Workaround PCIe IOMMU'able
Date: Wed, 26 Jun 2013 12:28:21 +0300 [thread overview]
Message-ID: <1372238906-9346-19-git-send-email-hdoyu@nvidia.com> (raw)
Make PCIe work as it is. IOMMU support can be implemented later.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
drivers/iommu/tegra-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 64da08a..6e82df3 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -402,6 +402,9 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,
for_each_set_bit(i, (unsigned long *)&map,
sizeof(map) * BITS_PER_BYTE) {
+ if (i == SWGID_AFI) /* FIXME: IOMMU'able PCIe */
+ continue;
+
offs = HWGRP_ASID_REG(i);
val = smmu_read(smmu, offs);
if (on) {
--
1.8.1.5
next reply other threads:[~2013-06-26 9:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-26 9:28 Hiroshi Doyu [this message]
2013-06-26 9:28 ` [PATCH 18/23] iommu/tegra: smmu: Workaround PCIe IOMMU'able Hiroshi Doyu
[not found] ` <1372238906-9346-19-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-06-26 11:06 ` Thierry Reding
2013-06-26 11:06 ` Thierry Reding
2013-06-26 11:09 ` Hiroshi Doyu
2013-06-26 11:09 ` Hiroshi Doyu
[not found] ` <20130626.140906.1216615781918366349.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-06-26 11:15 ` Thierry Reding
2013-06-26 11:15 ` Thierry Reding
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