From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>
Cc: Bryan Bell <bryan.j.bell@intel.com>,
Ben Widawsky <ben@bwidawsk.net>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: [PATCH 12/14] intel_l3_parity: Actually support multiple slices
Date: Tue, 17 Sep 2013 21:12:53 -0700 [thread overview]
Message-ID: <1379477575-2164-12-git-send-email-benjamin.widawsky@intel.com> (raw)
In-Reply-To: <1379477575-2164-1-git-send-email-benjamin.widawsky@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
tools/intel_l3_parity.c | 45 ++++++++++++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index c98eb80..ed7034a 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -41,19 +41,28 @@
static unsigned int devid;
/* L3 size is always a function of banks. The number of banks cannot be
* determined by number of slices however */
-#define MAX_BANKS 4
-#define NUM_BANKS \
- ((devid == PCI_CHIP_IVYBRIDGE_GT1 || devid == PCI_CHIP_IVYBRIDGE_M_GT1) ? 2 : 4)
+static inline int num_banks(void) {
+ if (IS_HSW_GT3(devid))
+ return 8; /* 4 per each slice */
+ else if (IS_HSW_GT1(devid) ||
+ devid == PCI_CHIP_IVYBRIDGE_GT1 ||
+ devid == PCI_CHIP_IVYBRIDGE_M_GT1)
+ return 2;
+ else
+ return 4;
+}
#define NUM_SUBBANKS 8
#define BYTES_PER_BANK (128 << 10)
/* Each row addresses [up to] 4b. This multiplied by the number of subbanks
* will give the L3 size per bank.
* TODO: Row size is fixed on IVB, and variable on HSW.*/
#define MAX_ROW (1<<12)
-#define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS * NUM_BANKS)
-#define NUM_REGS (NUM_BANKS * NUM_SUBBANKS)
-#define MAX_SLICES 1
-#define REAL_MAX_SLICES 1
+#define MAX_BANKS_PER_SLICE 4
+#define NUM_REGS (MAX_BANKS_PER_SLICE * NUM_SUBBANKS)
+#define MAX_SLICES (IS_HSW_GT3(devid) ? 2 : 1)
+#define REAL_MAX_SLICES 2
+/* TODO support SLM config */
+#define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS * num_banks())
struct __attribute__ ((__packed__)) l3_log_register {
uint32_t row0_enable : 1;
@@ -62,7 +71,7 @@ struct __attribute__ ((__packed__)) l3_log_register {
uint32_t row1_enable : 1;
uint32_t rsvd1 : 4;
uint32_t row1 : 11;
-} l3logs[REAL_MAX_SLICES][MAX_BANKS][NUM_SUBBANKS];
+} l3logs[REAL_MAX_SLICES][MAX_BANKS_PER_SLICE][NUM_SUBBANKS];
static int which_slice = -1;
#define for_each_slice(__i) \
@@ -74,16 +83,16 @@ static void dumpit(int slice)
{
int i, j;
- for (i = 0; i < NUM_BANKS; i++) {
+ for (i = 0; i < MAX_BANKS_PER_SLICE; i++) {
for (j = 0; j < NUM_SUBBANKS; j++) {
struct l3_log_register *reg = &l3logs[slice][i][j];
if (reg->row0_enable)
- printf("Row %d, Bank %d, Subbank %d is disabled\n",
- reg->row0, i, j);
+ printf("Slice %d, Row %d, Bank %d, Subbank %d is disabled\n",
+ slice, reg->row0, i, j);
if (reg->row1_enable)
- printf("Row %d, Bank %d, Subbank %d is disabled\n",
- reg->row1, i, j);
+ printf("Slice %d, Row %d, Bank %d, Subbank %d is disabled\n",
+ slice, reg->row1, i, j);
}
}
}
@@ -160,6 +169,8 @@ int main(int argc, char *argv[])
ret = asprintf(&path[0], "/sys/class/drm/card%d/l3_parity", device);
assert(ret != -1);
+ ret = asprintf(&path[1], "/sys/class/drm/card%d/l3_parity_slice_1", device);
+ assert(ret != -1);
for_each_slice(i) {
fd[i] = open(path[i], O_RDWR);
@@ -201,9 +212,9 @@ int main(int argc, char *argv[])
exit(EXIT_SUCCESS);
case 'H':
printf("Number of slices: %d\n", MAX_SLICES);
- printf("Number of banks: %d\n", NUM_BANKS);
+ printf("Number of banks: %d\n", num_banks());
printf("Subbanks per bank: %d\n", NUM_SUBBANKS);
- printf("L3 size: %dK\n", L3_SIZE >> 10);
+ printf("Max L3 size: %dK\n", L3_SIZE >> 10);
exit(EXIT_SUCCESS);
case 'r':
row = atoi(optarg);
@@ -212,7 +223,7 @@ int main(int argc, char *argv[])
break;
case 'b':
bank = atoi(optarg);
- if (bank >= NUM_BANKS)
+ if (bank >= num_banks() || bank >= MAX_BANKS_PER_SLICE)
exit(EXIT_FAILURE);
break;
case 's':
@@ -222,7 +233,7 @@ int main(int argc, char *argv[])
break;
case 'w':
which_slice = atoi(optarg);
- if (which_slice > 1)
+ if (which_slice >= MAX_SLICES)
exit(EXIT_FAILURE);
break;
case 'd':
--
1.8.4
next prev parent reply other threads:[~2013-09-18 4:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-18 4:12 [PATCH 1/6] drm/i915: Fix HSW parity test Ben Widawsky
2013-09-18 4:12 ` [PATCH 2/6] drm/i915: Add second slice l3 remapping Ben Widawsky
2013-09-18 7:36 ` Ville Syrjälä
2013-09-18 16:22 ` Ben Widawsky
2013-09-19 18:13 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 3/6] drm/i915: Make l3 remapping use the ring Ben Widawsky
2013-09-19 18:39 ` Daniel Vetter
2013-09-18 4:12 ` [PATCH 4/6] drm/i915: Keep a list of all contexts Ben Widawsky
2013-09-18 4:12 ` [PATCH 5/6] drm/i915: Do remaps for " Ben Widawsky
2013-09-18 7:48 ` Ville Syrjälä
2013-09-19 1:14 ` Ben Widawsky
2013-09-19 1:17 ` Ben Widawsky
2013-09-19 2:03 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 6/6] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF Ben Widawsky
2013-09-18 7:50 ` Ville Syrjälä
2013-09-19 17:47 ` [PATCH] [v2] " Ben Widawsky
2013-09-19 18:01 ` Ben Widawsky
2013-09-19 18:41 ` Daniel Vetter
2013-09-19 19:59 ` Ben Widawsky
2013-09-18 4:12 ` [PATCH 07/14] intel_l3_parity: Fix indentation Ben Widawsky
2013-09-18 4:12 ` [PATCH 08/14] intel_l3_parity: Assert all GEN7+ support Ben Widawsky
2013-09-18 4:12 ` [PATCH 09/14] intel_l3_parity: Use getopt for the l3 parity tool Ben Widawsky
2013-09-18 4:12 ` [PATCH 10/14] intel_l3_parity: Hardware info argument Ben Widawsky
2013-09-18 4:12 ` [PATCH 11/14] intel_l3_parity: slice support Ben Widawsky
2013-09-18 4:12 ` Ben Widawsky [this message]
2013-09-18 4:12 ` [PATCH 13/14] intel_l3_parity: Support error injection Ben Widawsky
2013-09-18 4:12 ` [PATCH 14/14] intel_l3_parity: Support a daemonic mode Ben Widawsky
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