From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: linux-edac-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC
Date: Mon, 30 Dec 2013 12:14:15 -0800 [thread overview]
Message-ID: <1388434457-4194-5-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1388434457-4194-1-git-send-email-sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 72 ++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..54de94b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,35 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait".
+ Value type: <prop-encoded-array>
+ Definition: L1/CPU error interrupt
+
+ - next-level-cache
+ Usage: optional
+ Value type: <phandle>
+ Definition: phandle pointing to the next level cache
+
+- cache node
+
+ Description: Describes a cache in an ARM based system
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: shall contain at least "cache"
+
+ - cache-level
+ Usage: required
+ Value type: <u32>
+ Definition: level in the cache heirachy
+
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait"
+ Value type: <prop-encoded-array>
+ Definition: the L2 error interrupt
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@@ -382,3 +411,46 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+
+Example 5 (Krait 32-bit system):
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <1 9 0xf04>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ interrupts = <0 2 0x4>;
+ };
+};
--
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hosted by The Linux Foundation
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WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC
Date: Mon, 30 Dec 2013 12:14:15 -0800 [thread overview]
Message-ID: <1388434457-4194-5-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1388434457-4194-1-git-send-email-sboyd@codeaurora.org>
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 72 ++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..54de94b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,35 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait".
+ Value type: <prop-encoded-array>
+ Definition: L1/CPU error interrupt
+
+ - next-level-cache
+ Usage: optional
+ Value type: <phandle>
+ Definition: phandle pointing to the next level cache
+
+- cache node
+
+ Description: Describes a cache in an ARM based system
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: shall contain at least "cache"
+
+ - cache-level
+ Usage: required
+ Value type: <u32>
+ Definition: level in the cache heirachy
+
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait"
+ Value type: <prop-encoded-array>
+ Definition: the L2 error interrupt
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@@ -382,3 +411,46 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+
+Example 5 (Krait 32-bit system):
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <1 9 0xf04>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ interrupts = <0 2 0x4>;
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org>
To: linux-edac@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC
Date: Mon, 30 Dec 2013 12:14:15 -0800 [thread overview]
Message-ID: <1388434457-4194-5-git-send-email-sboyd@codeaurora.org> (raw)
In-Reply-To: <1388434457-4194-1-git-send-email-sboyd@codeaurora.org>
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 72 ++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..54de94b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,35 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait".
+ Value type: <prop-encoded-array>
+ Definition: L1/CPU error interrupt
+
+ - next-level-cache
+ Usage: optional
+ Value type: <phandle>
+ Definition: phandle pointing to the next level cache
+
+- cache node
+
+ Description: Describes a cache in an ARM based system
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: shall contain at least "cache"
+
+ - cache-level
+ Usage: required
+ Value type: <u32>
+ Definition: level in the cache heirachy
+
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait"
+ Value type: <prop-encoded-array>
+ Definition: the L2 error interrupt
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@@ -382,3 +411,46 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+
+Example 5 (Krait 32-bit system):
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <1 9 0xf04>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ interrupts = <0 2 0x4>;
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2013-12-30 20:14 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-30 20:14 [PATCH v4 0/6] Krait L1/L2 EDAC driver Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2013-12-30 20:14 ` [PATCH v4 1/6] edac: Don't try to cancel workqueue when it's never setup Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-07 17:19 ` Borislav Petkov
2014-01-07 17:19 ` Borislav Petkov
2014-01-07 17:19 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 2/6] genirq: export percpu irq functions for module usage Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-07 23:02 ` Borislav Petkov
2014-01-07 23:02 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 3/6] ARM: Add Krait L2 accessor functions Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-07 23:07 ` Borislav Petkov
2014-01-07 23:07 ` Borislav Petkov
2014-01-07 23:09 ` Stephen Boyd
2014-01-07 23:09 ` Stephen Boyd
2014-01-09 0:53 ` Courtney Cavin
2014-01-09 0:53 ` Courtney Cavin
2014-01-09 1:54 ` Stephen Boyd
2014-01-09 1:54 ` Stephen Boyd
2014-01-09 11:03 ` Borislav Petkov
2014-01-09 11:03 ` Borislav Petkov
[not found] ` <1388434457-4194-1-git-send-email-sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2013-12-30 20:14 ` Stephen Boyd [this message]
2013-12-30 20:14 ` [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-07 10:54 ` Lorenzo Pieralisi
2014-01-07 10:54 ` Lorenzo Pieralisi
2014-01-07 20:12 ` Stephen Boyd
2014-01-07 20:12 ` Stephen Boyd
2014-01-08 10:05 ` Lorenzo Pieralisi
2014-01-08 10:05 ` Lorenzo Pieralisi
2014-01-09 20:52 ` Stephen Boyd
2014-01-09 20:52 ` Stephen Boyd
2014-01-10 10:54 ` Lorenzo Pieralisi
2014-01-10 10:54 ` Lorenzo Pieralisi
2013-12-30 20:14 ` [PATCH v4 5/6] edac: Add support for Krait CPU cache error detection Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-07 23:43 ` Borislav Petkov
2014-01-07 23:43 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 6/6] ARM: dts: msm: Add Krait CPU/L2 nodes Stephen Boyd
2013-12-30 20:14 ` Stephen Boyd
2014-01-04 10:19 ` [PATCH v4 0/6] Krait L1/L2 EDAC driver Borislav Petkov
2014-01-04 10:19 ` Borislav Petkov
[not found] ` <20140104101901.GA4439-K5JNixvcfoxupOikMc4+xw@public.gmane.org>
2014-01-06 22:09 ` Stephen Boyd
2014-01-06 22:09 ` Stephen Boyd
2014-01-06 22:09 ` Stephen Boyd
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