[PATCH 5/5] drm/i915: Add CxSR debugfs disabling

[jeff.mcgee@intel.com]

From: Jeff McGee <jeff.mcgee@intel.com>

i915_sr_disable:
'0' - CxSR enabled normally per device and settings.
'1' - CxSR explicitly disabled.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 43 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h     |  2 ++
 drivers/gpu/drm/i915/intel_pm.c     | 47 +++++++++++++++++++++----------------
 3 files changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 92f6213..cccb1bf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1523,6 +1523,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev))
 		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+	else if (IS_VALLEYVIEW(dev))
+		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	seq_printf(m, "self-refresh: %s\n",
 		   sr_enabled ? "enabled" : "disabled");
@@ -1530,6 +1532,46 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_sr_disable_get(void *data, u64 *val)
+{
+	struct drm_device *dev = data;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	*val = dev_priv->sr_disable;
+
+	return 0;
+}
+
+static int i915_sr_disable_set(void *data, u64 val)
+{
+	struct drm_device *dev = data;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+
+	if (dev_priv->sr_disable == (bool)val)
+		return 0;
+
+	drm_modeset_lock_all(dev);
+
+	DRM_DEBUG_DRIVER("Setting CxSR disable %s\n",
+			 val ? "true" : "false");
+
+	dev_priv->sr_disable = (bool)val;
+
+	/* Reset enabled crtc to force CxSR state update */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+		if (crtc->enabled)
+			intel_crtc_restore_mode(crtc);
+
+	drm_modeset_unlock_all(dev);
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_sr_disable_fops,
+			i915_sr_disable_get, i915_sr_disable_set,
+			"%llu\n");
+
 static int i915_emon_status(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3753,6 +3795,7 @@ static const struct i915_debugfs_files {
 	{"i915_rc6_disable", &i915_rc6_disable_fops},
 	{"i915_ips_disable", &i915_ips_disable_fops},
 	{"i915_fbc_disable", &i915_fbc_disable_fops},
+	{"i915_sr_disable", &i915_sr_disable_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
 	{"i915_ring_stop", &i915_ring_stop_fops},
 	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18b2849..6d7dae2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1537,6 +1537,8 @@ typedef struct drm_i915_private {
 
 	bool ips_disable;
 
+	bool sr_disable;
+
 	struct i915_power_domains power_domains;
 
 	struct i915_psr psr;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a8605fc..93e1c60 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1041,7 +1041,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
 	}
 
 	crtc = single_enabled_crtc(dev);
-	if (crtc) {
+	if (crtc && !dev_priv->sr_disable) {
 		const struct drm_display_mode *adjusted_mode;
 		int pixel_size = crtc->fb->bits_per_pixel / 8;
 		int clock;
@@ -1335,6 +1335,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		enabled |= 1 << PIPE_B;
 
 	if (single_plane_enabled(enabled) &&
+	    !dev_priv->sr_disable &&
 	    g4x_compute_srwm(dev, ffs(enabled) - 1,
 			     sr_latency_ns,
 			     &valleyview_wm_info,
@@ -1392,6 +1393,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
 		enabled |= 1 << PIPE_B;
 
 	if (single_plane_enabled(enabled) &&
+	    !dev_priv->sr_disable &&
 	    g4x_compute_srwm(dev, ffs(enabled) - 1,
 			     sr_latency_ns,
 			     &g4x_wm_info,
@@ -1433,7 +1435,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
 
 	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev);
-	if (crtc) {
+	if (crtc && !dev_priv->sr_disable) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 12000;
 		const struct drm_display_mode *adjusted_mode =
@@ -1603,7 +1605,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	I915_WRITE(FW_BLC2, fwater_hi);
 
 	if (HAS_FW_BLC(dev)) {
-		if (enabled) {
+		if (enabled && !dev_priv->sr_disable) {
 			if (IS_I945G(dev) || IS_I945GM(dev))
 				I915_WRITE(FW_BLC_SELF,
 					   FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
@@ -2279,12 +2281,34 @@ static void ilk_compute_wm_results(struct drm_device *dev,
 				   enum intel_ddb_partitioning partitioning,
 				   struct ilk_wm_values *results)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc;
 	int level, wm_lp;
 
 	results->enable_fbc_wm = merged->fbc_wm_enabled;
 	results->partitioning = partitioning;
 
+	/* LP0 register values */
+	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
+		enum pipe pipe = intel_crtc->pipe;
+		const struct intel_wm_level *r =
+			&intel_crtc->wm.active.wm[0];
+
+		if (WARN_ON(!r->enable))
+			continue;
+
+		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
+
+		results->wm_pipe[pipe] =
+			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
+			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
+			r->cur_val;
+	}
+
+	/* Leave LP1+ registers zeroed if self-refresh is not to be used */
+	if (dev_priv->sr_disable)
+		return;
+
 	/* LP1+ register values */
 	for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
 		const struct intel_wm_level *r;
@@ -2313,23 +2337,6 @@ static void ilk_compute_wm_results(struct drm_device *dev,
 		} else
 			results->wm_lp_spr[wm_lp - 1] = r->spr_val;
 	}
-
-	/* LP0 register values */
-	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
-		enum pipe pipe = intel_crtc->pipe;
-		const struct intel_wm_level *r =
-			&intel_crtc->wm.active.wm[0];
-
-		if (WARN_ON(!r->enable))
-			continue;
-
-		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
-
-		results->wm_pipe[pipe] =
-			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
-			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
-			r->cur_val;
-	}
 }
 
 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
-- 
1.8.5.2