From: Dario Faggioli <dario.faggioli@citrix.com>
To: George Dunlap <george.dunlap@eu.citrix.com>
Cc: Marcus Granado <Marcus.Granado@eu.citrix.com>,
Keir Fraser <keir@xen.org>, Tim Deegan <tim@xen.org>,
xen-devel@lists.xen.org, David Vrabel <david.vrabel@citrix.com>,
Jan Beulich <jbeulich@suse.com>
Subject: Re: [PATCH] credit: Change default timeslice to 5ms
Date: Thu, 6 Mar 2014 13:27:56 +0100 [thread overview]
Message-ID: <1394108876.16409.54.camel@Solace> (raw)
In-Reply-To: <5318644A.2060904@eu.citrix.com>
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On gio, 2014-03-06 at 12:04 +0000, George Dunlap wrote:
> On 03/05/2014 05:18 PM, David Vrabel wrote:
> > On 05/03/14 16:29, George Dunlap wrote:
> >> --- a/xen/common/sched_credit.c
> >> +++ b/xen/common/sched_credit.c
> >> @@ -29,9 +29,9 @@
> >> * Basic constants
> >> */
> >> #define CSCHED_DEFAULT_WEIGHT 256
> >> -#define CSCHED_TICKS_PER_TSLICE 3
> >> -/* Default timeslice: 30ms */
> >> -#define CSCHED_DEFAULT_TSLICE_MS 30
> >> +#define CSCHED_TICKS_PER_TSLICE 1
> > The TICKS_PER_TSLICE change doubles the tick rate. Is this intentional?
> > It's not mentioned in the commit message.
>
> Hmm -- actually, I just realized that Marcus' test was done with 3 ticks
> per timeslice, so "5ms / 1 tick" has *not* been validated. And this is
> actually important, because the main purpose of the ticks is to give the
> scheduler an opportunity to switch VMs out of "BOOST" priority and into
> "UNDER" priority. Reducing the ticks per timeslice changes that
> dynamic, and would need to be tested separately.
>
Which is even higher tick frequency, isn't it? Anyway, you're right, we
should go for the tested solution.
> Also, I just discovered a rather pathological case in general that seems
> to be in the scheduler, so for the time being let me retract this while
> I figure that out.
>
Care to share some more details about this?
Regards,
Dario
--
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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next prev parent reply other threads:[~2014-03-06 12:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-05 16:29 [PATCH] credit: Change default timeslice to 5ms George Dunlap
2014-03-05 16:33 ` Dario Faggioli
2014-03-05 17:18 ` David Vrabel
2014-03-05 18:04 ` Dario Faggioli
2014-03-06 12:04 ` George Dunlap
2014-03-06 12:27 ` Dario Faggioli [this message]
2014-03-06 10:39 ` Tim Deegan
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