* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit @ 2014-04-28 23:11 Fabio Estevam 2014-04-28 23:40 ` Otavio Salvador 0 siblings, 1 reply; 6+ messages in thread From: Fabio Estevam @ 2014-04-28 23:11 UTC (permalink / raw) To: u-boot From: Fabio Estevam <fabio.estevam@freescale.com> On mx6sl there is a LVE (Low Voltage Enable) in the IOMUXC_SW_PAD_CTL register. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as bit 17 as this bit is unused and fits the current MUX_PAD_CTRL_MASK mask. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/imx-common/iomux-v3.c | 8 ++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802..6e46ea8 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..6d3561f 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t; #ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_LVE (1 << 17) +#define PAD_CTL_LVE_BIT (1 << 22) #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit 2014-04-28 23:11 [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit Fabio Estevam @ 2014-04-28 23:40 ` Otavio Salvador 2014-04-29 0:14 ` Fabio Estevam 0 siblings, 1 reply; 6+ messages in thread From: Otavio Salvador @ 2014-04-28 23:40 UTC (permalink / raw) To: u-boot On Mon, Apr 28, 2014 at 8:11 PM, Fabio Estevam <festevam@gmail.com> wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > On mx6sl there is a LVE (Low Voltage Enable) in the IOMUXC_SW_PAD_CTL register. > > LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the > calculation easier we can define it as bit 17 as this bit is unused and fits the > current MUX_PAD_CTRL_MASK mask. > > Add support for it. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > arch/arm/imx-common/iomux-v3.c | 8 ++++++++ > arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c > index b59b802..6e46ea8 100644 > --- a/arch/arm/imx-common/iomux-v3.c > +++ b/arch/arm/imx-common/iomux-v3.c > @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) > (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; > u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; > > +#if defined CONFIG_MX6SL > + /* Check whether LVE bit needs to be set */ > + if (pad_ctrl & PAD_CTL_LVE) { > + pad_ctrl &= ~PAD_CTL_LVE; > + pad_ctrl |= PAD_CTL_LVE_BIT; > + } > +#endif > + > if (mux_ctrl_ofs) > __raw_writel(mux_mode, base + mux_ctrl_ofs); > > diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h > index dec11a1..6d3561f 100644 > --- a/arch/arm/include/asm/imx-common/iomux-v3.h > +++ b/arch/arm/include/asm/imx-common/iomux-v3.h > @@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t; > #ifdef CONFIG_MX6 > > #define PAD_CTL_HYS (1 << 16) > +#define PAD_CTL_LVE (1 << 17) > +#define PAD_CTL_LVE_BIT (1 << 22) This conflicts with: #define NO_PAD_CTRL (1 << 17) I have changed the MASK as: -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x43ffff << MUX_PAD_CTRL_SHIFT) and seems to work fine. Do you see any issue? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit 2014-04-28 23:40 ` Otavio Salvador @ 2014-04-29 0:14 ` Fabio Estevam 2014-04-29 0:27 ` Otavio Salvador 0 siblings, 1 reply; 6+ messages in thread From: Fabio Estevam @ 2014-04-29 0:14 UTC (permalink / raw) To: u-boot On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador <otavio@ossystems.com.br> wrote: >> #define PAD_CTL_HYS (1 << 16) >> +#define PAD_CTL_LVE (1 << 17) >> +#define PAD_CTL_LVE_BIT (1 << 22) > > This conflicts with: > > #define NO_PAD_CTRL (1 << 17) Correct, I missed the NO_PAD_CTRL definition. > > I have changed the MASK as: > > -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) > +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x43ffff << MUX_PAD_CTRL_SHIFT) > > and seems to work fine. Do you see any issue? Changing this mask will alter the layout of the bitfield definitions and will affect the other fields: * * IOMUX/PAD Bit field definitions * * MUX_CTRL_OFS: 0..11 (12) * PAD_CTRL_OFS: 12..23 (12) * SEL_INPUT_OFS: 24..35 (12) * MUX_MODE + SION: 36..40 (5) * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) * SEL_INP: 59..62 (4) * reserved: 63 (1) */ ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit 2014-04-29 0:14 ` Fabio Estevam @ 2014-04-29 0:27 ` Otavio Salvador 2014-04-29 2:53 ` Fabio Estevam 0 siblings, 1 reply; 6+ messages in thread From: Otavio Salvador @ 2014-04-29 0:27 UTC (permalink / raw) To: u-boot On Mon, Apr 28, 2014 at 9:14 PM, Fabio Estevam <festevam@gmail.com> wrote: > On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador > <otavio@ossystems.com.br> wrote: >>> #define PAD_CTL_HYS (1 << 16) >>> +#define PAD_CTL_LVE (1 << 17) >>> +#define PAD_CTL_LVE_BIT (1 << 22) >> >> This conflicts with: >> >> #define NO_PAD_CTRL (1 << 17) > > Correct, I missed the NO_PAD_CTRL definition. So use 18? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit 2014-04-29 0:27 ` Otavio Salvador @ 2014-04-29 2:53 ` Fabio Estevam 2014-04-29 12:07 ` Fabio Estevam 0 siblings, 1 reply; 6+ messages in thread From: Fabio Estevam @ 2014-04-29 2:53 UTC (permalink / raw) To: u-boot On Mon, Apr 28, 2014 at 9:27 PM, Otavio Salvador <otavio@ossystems.com.br> wrote: > On Mon, Apr 28, 2014 at 9:14 PM, Fabio Estevam <festevam@gmail.com> wrote: >> On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador >> <otavio@ossystems.com.br> wrote: >>>> #define PAD_CTL_HYS (1 << 16) >>>> +#define PAD_CTL_LVE (1 << 17) >>>> +#define PAD_CTL_LVE_BIT (1 << 22) >>> >>> This conflicts with: >>> >>> #define NO_PAD_CTRL (1 << 17) >> >> Correct, I missed the NO_PAD_CTRL definition. > > So use 18? It would also break the existing IOMUX config layout. Bit 63 is free, so I came up with this change: diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802..45abee1 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -20,6 +20,13 @@ static void *base = (void *)IOMUXC_BASE_ADDR; */ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) { +#if defined CONFIG_MX6SL + bool lve = false; + + if(pad & PAD_CTL_LVE) + lve = true; +#endif + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; u32 sel_input_ofs = @@ -30,6 +37,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (lve) + pad_ctrl |= PAD_CTL_LVE_BIT; +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..5999552 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -42,7 +42,7 @@ * MUX_MODE + SION: 36..40 (5) * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) * SEL_INP: 59..62 (4) - * reserved: 63 (1) + * LVE: 63 (1) */ typedef u64 iomux_v3_cfg_t; @@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t; #ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_LVE 0x8000000000000000 +#define PAD_CTL_LVE_BIT (1 << 22) #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) ,and in order to declare a pin as LVE we would need to do this in the board file: MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL) | PAD_CTL_LVE, What do you think? ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit 2014-04-29 2:53 ` Fabio Estevam @ 2014-04-29 12:07 ` Fabio Estevam 0 siblings, 0 replies; 6+ messages in thread From: Fabio Estevam @ 2014-04-29 12:07 UTC (permalink / raw) To: u-boot Otavio, On Mon, Apr 28, 2014 at 11:53 PM, Fabio Estevam <festevam@gmail.com> wrote: >> So use 18? > > It would also break the existing IOMUX config layout. > > Bit 63 is free, so I came up with this change: Please discard this one. Actually I have a better proposal now and will submit the new patch for you to try later today. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-04-29 12:07 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-04-28 23:11 [U-Boot] [PATCH] iomux-v3: Add support for mx6sl LVE bit Fabio Estevam 2014-04-28 23:40 ` Otavio Salvador 2014-04-29 0:14 ` Fabio Estevam 2014-04-29 0:27 ` Otavio Salvador 2014-04-29 2:53 ` Fabio Estevam 2014-04-29 12:07 ` Fabio Estevam
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