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From: dinguyen@altera.com (Dinh Nguyen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk
Date: Wed, 18 Jun 2014 11:14:32 -0500	[thread overview]
Message-ID: <1403108072.15124.0.camel@linux-builds1> (raw)
In-Reply-To: <20140617221138.32686.1282@quantum>

Hi Mike,

On Tue, 2014-06-17 at 15:11 -0700, Mike Turquette wrote:
> Quoting dinguyen at altera.com (2014-06-13 20:00:35)
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > The debug base clock can be bypassed from the main PLL to the OSC1 clock.
> > The bypass register is the staysoc1(0x10) register that is in the clock
> > manager.
> > 
> > This patch adds the option to get the correct parent for the debug base
> > clock.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> 
> Looks good to me.
> 
> Regards,
> Mike

Thanks for reviewing. Can you please apply it to your for-next?

Dinh

  reply	other threads:[~2014-06-18 16:14 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-14  3:00 [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk dinguyen at altera.com
2014-06-17 22:11 ` Mike Turquette
2014-06-18 16:14   ` Dinh Nguyen [this message]
  -- strict thread matches above, loose matches on Subject: below --
2015-07-25  3:30 dinguyen
2015-08-11 23:54 ` Stephen Boyd

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