From: Stephen Boyd <sboyd@codeaurora.org>
To: dinguyen@opensource.altera.com
Cc: mturquette@baylibre.com, dinh.linux@gmail.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk
Date: Tue, 11 Aug 2015 16:54:52 -0700 [thread overview]
Message-ID: <20150811235451.GA26614@codeaurora.org> (raw)
In-Reply-To: <1437795018-27601-1-git-send-email-dinguyen@opensource.altera.com>
On 07/24, dinguyen@opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>
> The debug base clock can be bypassed from the main PLL to the OSC1 clock.
> The bypass register is the staysoc1(0x10) register that is in the clock
> manager.
>
> This patch adds the option to get the correct parent for the debug base
> clock.
>
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-08-11 23:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-25 3:30 [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk dinguyen
2015-08-11 23:54 ` Stephen Boyd [this message]
-- strict thread matches above, loose matches on Subject: below --
2014-06-14 3:00 dinguyen at altera.com
2014-06-17 22:11 ` Mike Turquette
2014-06-18 16:14 ` Dinh Nguyen
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