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From: tthayer@opensource.altera.com (tthayer at opensource.altera.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 3/5] edac: altera: Remove SDRAM module compile
Date: Thu, 30 Oct 2014 10:32:09 -0500	[thread overview]
Message-ID: <1414683131-20786-4-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1414683131-20786-1-git-send-email-tthayer@opensource.altera.com>

From: Thor Thayer <tthayer@opensource.altera.com>

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v3: Added in this version as a separate patch.
---
 drivers/edac/Kconfig |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7072c28..1719975 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
 	  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-	tristate "Altera SDRAM Memory Controller EDAC"
-	depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+	bool "Altera SDRAM Memory Controller EDAC"
+	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
 	help
 	  Support for error detection and correction on the
 	  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: <tthayer@opensource.altera.com>
To: bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
	robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
	grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com,
	tthayer@opensource.altera.com
Subject: [PATCHv3 3/5] edac: altera: Remove SDRAM module compile
Date: Thu, 30 Oct 2014 10:32:09 -0500	[thread overview]
Message-ID: <1414683131-20786-4-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1414683131-20786-1-git-send-email-tthayer@opensource.altera.com>

From: Thor Thayer <tthayer@opensource.altera.com>

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v3: Added in this version as a separate patch.
---
 drivers/edac/Kconfig |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7072c28..1719975 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
 	  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-	tristate "Altera SDRAM Memory Controller EDAC"
-	depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+	bool "Altera SDRAM Memory Controller EDAC"
+	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
 	help
 	  Support for error detection and correction on the
 	  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: <tthayer@opensource.altera.com>
To: <bp@alien8.de>, <dougthompson@xmission.com>,
	<m.chehab@samsung.com>, <robh+dt@kernel.org>,
	<pawel.moll@arm.com>, <mark.rutland@arm.com>,
	<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
	<linux@arm.linux.org.uk>, <dinguyen@opensource.altera.com>,
	<grant.likely@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
	<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <tthayer.linux@gmail.com>,
	<tthayer@opensource.altera.com>
Subject: [PATCHv3 3/5] edac: altera: Remove SDRAM module compile
Date: Thu, 30 Oct 2014 10:32:09 -0500	[thread overview]
Message-ID: <1414683131-20786-4-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1414683131-20786-1-git-send-email-tthayer@opensource.altera.com>

From: Thor Thayer <tthayer@opensource.altera.com>

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v3: Added in this version as a separate patch.
---
 drivers/edac/Kconfig |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7072c28..1719975 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
 	  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-	tristate "Altera SDRAM Memory Controller EDAC"
-	depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+	bool "Altera SDRAM Memory Controller EDAC"
+	depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
 	help
 	  Support for error detection and correction on the
 	  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5


  parent reply	other threads:[~2014-10-30 15:32 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-30 15:32 [PATCHv3 0/5] Add Altera peripheral memories to EDAC framework tthayer at opensource.altera.com
2014-10-30 15:32 ` tthayer
2014-10-30 15:32 ` tthayer
2014-10-30 15:32 ` [PATCHv3 1/5] arm: socfpga: Enable L2 Cache ECC on startup tthayer at opensource.altera.com
2014-10-30 15:32   ` tthayer
2014-10-30 15:32   ` tthayer
2014-10-30 15:32 ` [PATCHv3 2/5] arm: socfpga: Enable OCRAM " tthayer at opensource.altera.com
2014-10-30 15:32   ` tthayer
2014-10-30 15:32   ` tthayer
2014-10-30 15:32 ` tthayer at opensource.altera.com [this message]
2014-10-30 15:32   ` [PATCHv3 3/5] edac: altera: Remove SDRAM module compile tthayer
2014-10-30 15:32   ` tthayer
2014-10-30 15:32 ` [PATCHv3 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support tthayer at opensource.altera.com
2014-10-30 15:32   ` tthayer
2014-10-30 15:32   ` tthayer
2014-11-04 15:12   ` Borislav Petkov
2014-11-04 15:12     ` Borislav Petkov
2014-11-04 22:57     ` Thor Thayer
2014-11-04 22:57       ` Thor Thayer
2014-11-04 22:57       ` Thor Thayer
2014-11-06 16:31       ` Borislav Petkov
2014-11-06 16:31         ` Borislav Petkov
2014-11-07 16:31         ` Dinh Nguyen
2014-11-07 16:31           ` Dinh Nguyen
2014-11-07 16:31           ` Dinh Nguyen
2014-11-07 16:51           ` Borislav Petkov
2014-11-07 16:51             ` Borislav Petkov
2014-11-07 16:51             ` Borislav Petkov
2014-10-30 15:32 ` [PATCHv3 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC tthayer at opensource.altera.com
2014-10-30 15:32   ` tthayer
2014-10-30 15:32   ` tthayer

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