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From: Yingjoe Chen <yingjoe.chen@mediatek.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Jiang Liu <jiang.liu@linux.intel.com>,
	Marc Zyngier <Marc.Zyngier@arm.com>,
	Boris BREZILLON <boris.brezillon@free-electrons.com>,
	Russell King <linux@arm.linux.org.uk>,
	Jason Cooper <jason@lakedaemon.net>,
	Pawel Moll <Pawel.Moll@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"hc.yen@mediatek.com" <hc.yen@mediatek.com>,
	"srv_heupstream@mediatek.com" <srv_heupstream@mediatek.com>,
	"yh.chen@mediatek.com" <yh.chen@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"grant.likely@linaro.org" <grant.likely@linaro.org>,
	Yijing Wang <wangyijing@huawei.com>,
	Rob Herring <robh+dt@kernel.org>,
	"nathan.chung@mediatek.com" <nathan.chung@mediatek.com>,
	"yingjoe.chen@gmail.com" <yingjoe.chen@gmail.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"eddie.huang@mediatek.com" <eddie.huang@mediatek.co>
Subject: Re: [PATCH v7 2/4] ARM: mediatek: Add sysirq interrupt polarity support
Date: Fri, 21 Nov 2014 23:36:07 +0800	[thread overview]
Message-ID: <1416584167.24971.9.camel@mtksdaap41> (raw)
In-Reply-To: <20141119180448.GD12851@leverpostej>

Hi Mark,


On Wed, 2014-11-19 at 18:04 +0000, Mark Rutland wrote:
> On Wed, Nov 19, 2014 at 02:14:09PM +0000, Yingjoe Chen wrote:
> > +	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> > +		if (type == IRQ_TYPE_LEVEL_LOW)
> > +			type = IRQ_TYPE_LEVEL_HIGH;
> > +		else
> > +			type = IRQ_TYPE_EDGE_RISING;
> > +		value |= (1 << offset);
> > +	} else
> > +		value &= ~(1 << offset);
> 
> Nit: if one branch of an if statements is bracketed, both branches
> should be. Please bracket the else case.

OK, will change in next version.

> > +	writel(value, chip_data->intpol_base + reg_index * 4);
> > +
> > +	data = data->parent_data;
> > +	ret = data->chip->irq_set_type(data, type);
> > +	spin_unlock_irqrestore(&chip_data->lock, flags);
> > +	return ret;
> > +}
> > +
> > +static struct irq_chip mtk_sysirq_chip = {
> > +	.name			= "MT_SYSIRQ",
> > +	.irq_mask		= irq_chip_mask_parent,
> > +	.irq_unmask		= irq_chip_unmask_parent,
> > +	.irq_eoi		= irq_chip_eoi_parent,
> > +	.irq_set_type		= mtk_sysirq_set_type,
> > +	.irq_retrigger		= irq_chip_retrigger_hierarchy,
> > +	.irq_set_affinity	= irq_chip_set_affinity_parent,
> > +};
> > +
> > +static int mtk_sysirq_domain_xlate(struct irq_domain *d,
> > +				   struct device_node *controller,
> > +				   const u32 *intspec, unsigned int intsize,
> > +				   unsigned long *out_hwirq,
> > +				   unsigned int *out_type)
> > +{
> > +	if (intsize < 3)
> > +		return -EINVAL;
> > +
> > +	/* sysirq doesn't support PPI */
> > +	if (intspec[0])
> > +		return -EINVAL;
> > +
> > +	*out_hwirq = intspec[1];
> > +	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
> 
> All of this is very strongly tied to the GIC, but the binding made it
> sound like this was more generic (it didn't specify the number of cells
> or their meaning). It doesn't look like we validate that this is
> attached to a GIC.
> 
> Do we expect this to only ever be attached to a GICv2?
> 
> It would be nice to either make this generic or to describe the format
> in the binding.

This expect the parent to use the same interrupt cells format as GIC.
I'll fix the binding to make this more clear.

> Also, surely you expect intsize == 3 if you expect a GICv2? Likewise in
> mtk_sysirq_domain_alloc.

OK, will change that in next version.

Joe.C

WARNING: multiple messages have this Message-ID (diff)
From: Yingjoe Chen <yingjoe.chen@mediatek.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Jiang Liu <jiang.liu@linux.intel.com>,
	Marc Zyngier <Marc.Zyngier@arm.com>,
	Boris BREZILLON <boris.brezillon@free-electrons.com>,
	Russell King <linux@arm.linux.org.uk>,
	Jason Cooper <jason@lakedaemon.net>,
	Pawel Moll <Pawel.Moll@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"hc.yen@mediatek.com" <hc.yen@mediatek.com>,
	"srv_heupstream@mediatek.com" <srv_heupstream@mediatek.com>,
	"yh.chen@mediatek.com" <yh.chen@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"grant.likely@linaro.org" <grant.likely@linaro.org>,
	Yijing Wang <wangyijing@huawei.com>,
	Rob Herring <robh+dt@kernel.org>,
	"nathan.chung@mediatek.com" <nathan.chung@mediatek.com>,
	"yingjoe.chen@gmail.com" <yingjoe.chen@gmail.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"eddie.huang@mediatek.com" <eddie.huang@mediatek.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Sascha Hauer <kernel@pengutronix.de>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v7 2/4] ARM: mediatek: Add sysirq interrupt polarity support
Date: Fri, 21 Nov 2014 23:36:07 +0800	[thread overview]
Message-ID: <1416584167.24971.9.camel@mtksdaap41> (raw)
In-Reply-To: <20141119180448.GD12851@leverpostej>

Hi Mark,


On Wed, 2014-11-19 at 18:04 +0000, Mark Rutland wrote:
> On Wed, Nov 19, 2014 at 02:14:09PM +0000, Yingjoe Chen wrote:
> > +	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> > +		if (type == IRQ_TYPE_LEVEL_LOW)
> > +			type = IRQ_TYPE_LEVEL_HIGH;
> > +		else
> > +			type = IRQ_TYPE_EDGE_RISING;
> > +		value |= (1 << offset);
> > +	} else
> > +		value &= ~(1 << offset);
> 
> Nit: if one branch of an if statements is bracketed, both branches
> should be. Please bracket the else case.

OK, will change in next version.

> > +	writel(value, chip_data->intpol_base + reg_index * 4);
> > +
> > +	data = data->parent_data;
> > +	ret = data->chip->irq_set_type(data, type);
> > +	spin_unlock_irqrestore(&chip_data->lock, flags);
> > +	return ret;
> > +}
> > +
> > +static struct irq_chip mtk_sysirq_chip = {
> > +	.name			= "MT_SYSIRQ",
> > +	.irq_mask		= irq_chip_mask_parent,
> > +	.irq_unmask		= irq_chip_unmask_parent,
> > +	.irq_eoi		= irq_chip_eoi_parent,
> > +	.irq_set_type		= mtk_sysirq_set_type,
> > +	.irq_retrigger		= irq_chip_retrigger_hierarchy,
> > +	.irq_set_affinity	= irq_chip_set_affinity_parent,
> > +};
> > +
> > +static int mtk_sysirq_domain_xlate(struct irq_domain *d,
> > +				   struct device_node *controller,
> > +				   const u32 *intspec, unsigned int intsize,
> > +				   unsigned long *out_hwirq,
> > +				   unsigned int *out_type)
> > +{
> > +	if (intsize < 3)
> > +		return -EINVAL;
> > +
> > +	/* sysirq doesn't support PPI */
> > +	if (intspec[0])
> > +		return -EINVAL;
> > +
> > +	*out_hwirq = intspec[1];
> > +	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
> 
> All of this is very strongly tied to the GIC, but the binding made it
> sound like this was more generic (it didn't specify the number of cells
> or their meaning). It doesn't look like we validate that this is
> attached to a GIC.
> 
> Do we expect this to only ever be attached to a GICv2?
> 
> It would be nice to either make this generic or to describe the format
> in the binding.

This expect the parent to use the same interrupt cells format as GIC.
I'll fix the binding to make this more clear.

> Also, surely you expect intsize == 3 if you expect a GICv2? Likewise in
> mtk_sysirq_domain_alloc.

OK, will change that in next version.

Joe.C



WARNING: multiple messages have this Message-ID (diff)
From: yingjoe.chen@mediatek.com (Yingjoe Chen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 2/4] ARM: mediatek: Add sysirq interrupt polarity support
Date: Fri, 21 Nov 2014 23:36:07 +0800	[thread overview]
Message-ID: <1416584167.24971.9.camel@mtksdaap41> (raw)
In-Reply-To: <20141119180448.GD12851@leverpostej>

Hi Mark,


On Wed, 2014-11-19 at 18:04 +0000, Mark Rutland wrote:
> On Wed, Nov 19, 2014 at 02:14:09PM +0000, Yingjoe Chen wrote:
> > +	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
> > +		if (type == IRQ_TYPE_LEVEL_LOW)
> > +			type = IRQ_TYPE_LEVEL_HIGH;
> > +		else
> > +			type = IRQ_TYPE_EDGE_RISING;
> > +		value |= (1 << offset);
> > +	} else
> > +		value &= ~(1 << offset);
> 
> Nit: if one branch of an if statements is bracketed, both branches
> should be. Please bracket the else case.

OK, will change in next version.

> > +	writel(value, chip_data->intpol_base + reg_index * 4);
> > +
> > +	data = data->parent_data;
> > +	ret = data->chip->irq_set_type(data, type);
> > +	spin_unlock_irqrestore(&chip_data->lock, flags);
> > +	return ret;
> > +}
> > +
> > +static struct irq_chip mtk_sysirq_chip = {
> > +	.name			= "MT_SYSIRQ",
> > +	.irq_mask		= irq_chip_mask_parent,
> > +	.irq_unmask		= irq_chip_unmask_parent,
> > +	.irq_eoi		= irq_chip_eoi_parent,
> > +	.irq_set_type		= mtk_sysirq_set_type,
> > +	.irq_retrigger		= irq_chip_retrigger_hierarchy,
> > +	.irq_set_affinity	= irq_chip_set_affinity_parent,
> > +};
> > +
> > +static int mtk_sysirq_domain_xlate(struct irq_domain *d,
> > +				   struct device_node *controller,
> > +				   const u32 *intspec, unsigned int intsize,
> > +				   unsigned long *out_hwirq,
> > +				   unsigned int *out_type)
> > +{
> > +	if (intsize < 3)
> > +		return -EINVAL;
> > +
> > +	/* sysirq doesn't support PPI */
> > +	if (intspec[0])
> > +		return -EINVAL;
> > +
> > +	*out_hwirq = intspec[1];
> > +	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
> 
> All of this is very strongly tied to the GIC, but the binding made it
> sound like this was more generic (it didn't specify the number of cells
> or their meaning). It doesn't look like we validate that this is
> attached to a GIC.
> 
> Do we expect this to only ever be attached to a GICv2?
> 
> It would be nice to either make this generic or to describe the format
> in the binding.

This expect the parent to use the same interrupt cells format as GIC.
I'll fix the binding to make this more clear.

> Also, surely you expect intsize == 3 if you expect a GICv2? Likewise in
> mtk_sysirq_domain_alloc.

OK, will change that in next version.

Joe.C

  reply	other threads:[~2014-11-21 15:36 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-19 14:14 [PATCH v7 0/4] ARM: mediatek: Add support for interrupt polarity Yingjoe Chen
2014-11-19 14:14 ` Yingjoe Chen
2014-11-19 14:14 ` Yingjoe Chen
2014-11-19 14:14 ` [PATCH v7 1/4] irqchip: gic: Support hierarchy irq domain Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
2014-11-19 17:18   ` Marc Zyngier
2014-11-19 17:18     ` Marc Zyngier
2014-11-19 17:18     ` Marc Zyngier
     [not found]     ` <87h9xvaz2p.fsf-BgpFEFc6EmV6Fr0h90IsVGS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2014-11-20  3:57       ` Yingjoe Chen
2014-11-20  3:57         ` Yingjoe Chen
2014-11-20  3:57         ` Yingjoe Chen
2014-11-20  9:41         ` Yingjoe Chen
2014-11-20  9:41           ` Yingjoe Chen
2014-11-20  9:41           ` Yingjoe Chen
2014-11-20 10:29           ` Marc Zyngier
2014-11-20 10:29             ` Marc Zyngier
2014-11-20 10:29             ` Marc Zyngier
2014-11-20  4:26       ` Jiang Liu
2014-11-20  4:26         ` Jiang Liu
2014-11-20  4:26         ` Jiang Liu
     [not found]         ` <546D6D62.4030005-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2014-11-20 10:07           ` Marc Zyngier
2014-11-20 10:07             ` Marc Zyngier
2014-11-20 10:07             ` Marc Zyngier
     [not found]             ` <87wq6q9odi.fsf-BgpFEFc6EmV6Fr0h90IsVGS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2014-11-21 15:51               ` Yingjoe Chen
2014-11-21 15:51                 ` Yingjoe Chen
2014-11-21 15:51                 ` Yingjoe Chen
2014-11-24 19:31                 ` Marc Zyngier
2014-11-24 19:31                   ` Marc Zyngier
2014-11-24 19:31                   ` Marc Zyngier
2014-11-19 14:14 ` [PATCH v7 2/4] ARM: mediatek: Add sysirq interrupt polarity support Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
     [not found]   ` <1416406451-4578-3-git-send-email-yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-11-19 18:04     ` Mark Rutland
2014-11-19 18:04       ` Mark Rutland
2014-11-19 18:04       ` Mark Rutland
2014-11-21 15:36       ` Yingjoe Chen [this message]
2014-11-21 15:36         ` Yingjoe Chen
2014-11-21 15:36         ` Yingjoe Chen
2014-11-19 14:14 ` [PATCH v7 3/4] ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
     [not found]   ` <1416406451-4578-4-git-send-email-yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-11-19 17:49     ` Marc Zyngier
2014-11-19 17:49       ` Marc Zyngier
2014-11-19 17:49       ` Marc Zyngier
2014-11-20  3:29       ` Yingjoe Chen
2014-11-20  3:29         ` Yingjoe Chen
2014-11-20  3:29         ` Yingjoe Chen
2014-11-19 14:14 ` [PATCH v7 4/4] dt-bindings: add bindings for mediatek sysirq Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
2014-11-19 14:14   ` Yingjoe Chen
     [not found]   ` <1416406451-4578-5-git-send-email-yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2014-11-19 18:07     ` Mark Rutland
2014-11-19 18:07       ` Mark Rutland
2014-11-19 18:07       ` Mark Rutland
2014-11-24 15:14       ` Yingjoe Chen
2014-11-24 15:14         ` Yingjoe Chen
2014-11-24 15:14         ` Yingjoe Chen

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