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From: James Bottomley <James.Bottomley@HansenPartnership.com>
To: Helge Deller <deller@gmx.de>
Cc: linux-parisc@vger.kernel.org, ohn David Anglin <dave.anglin@bell.net>
Subject: Re: [PATCH] parisc: Align locks for LWS syscalls to L1 cache size
Date: Wed, 02 Sep 2015 14:32:41 -0700	[thread overview]
Message-ID: <1441229561.2259.18.camel@HansenPartnership.com> (raw)
In-Reply-To: <20150902193840.GA4499@ls3530.box>

On Wed, 2015-09-02 at 21:38 +0200, Helge Deller wrote:
> Align the locks for the Light weight syscall (LWS) which is used for
> atomic userspace operations (e.g. gcc atomic builtins) on L1 cache
> boundaries. This should speed up LWS calls on PA20 systems.

Is there any evidence for this?  The architectural requirement for ldcw
on which all this is based is pegged at 16 bytes.  This implies that the
burst width on PA88/89 may indeed be 128 bytes, but the coherence width
for operations may still be 16 bytes.  If that speculation is true,
there's no speed at all gained by aligning ldcw to 128 bytes and all you
do is waste space.

James



  parent reply	other threads:[~2015-09-02 21:32 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-02 19:38 [PATCH] parisc: Align locks for LWS syscalls to L1 cache size Helge Deller
2015-09-02 19:46 ` John David Anglin
2015-09-02 20:29   ` Helge Deller
2015-09-05 21:48     ` Helge Deller
2015-09-07 20:51       ` Helge Deller
2015-09-02 21:32 ` James Bottomley [this message]
2015-09-02 22:18   ` Helge Deller

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