Patch "drm/amdgpu: fix IH ring allocation for bus addresses (v2)" has been added to the 4.2-stable tree

Patch "drm/amdgpu: fix IH ring allocation for bus addresses (v2)" has been added to the 4.2-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    drm/amdgpu: fix IH ring allocation for bus addresses (v2)

to the 4.2-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch
and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From 52293c67f1e7542a6dc61037d83c266e216bef27 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 24 Aug 2015 22:46:13 -0400
Subject: drm/amdgpu: fix IH ring allocation for bus addresses (v2)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

From: Alex Deucher <alexander.deucher@amd.com>

commit 52293c67f1e7542a6dc61037d83c266e216bef27 upstream.

Use pci_alloc_consistent rather than kzalloc since we
need 256 byte aligned memory for the ring buffer.

v2: fix copy paste typo in free function noticed
by Jammy.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=91749

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c |   20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -97,18 +97,12 @@ int amdgpu_ih_ring_init(struct amdgpu_de
 			/* add 8 bytes for the rptr/wptr shadows and
 			 * add them to the end of the ring allocation.
 			 */
-			adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
+			adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
+								 adev->irq.ih.ring_size + 8,
+								 &adev->irq.ih.rb_dma_addr);
 			if (adev->irq.ih.ring == NULL)
 				return -ENOMEM;
-			adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
-								  (void *)adev->irq.ih.ring,
-								  adev->irq.ih.ring_size,
-								  PCI_DMA_BIDIRECTIONAL);
-			if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) {
-				dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n");
-				kfree((void *)adev->irq.ih.ring);
-				return -ENOMEM;
-			}
+			memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
 			adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
 			adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
 		}
@@ -148,9 +142,9 @@ void amdgpu_ih_ring_fini(struct amdgpu_d
 			/* add 8 bytes for the rptr/wptr shadows and
 			 * add them to the end of the ring allocation.
 			 */
-			pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr,
-					 adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL);
-			kfree((void *)adev->irq.ih.ring);
+			pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
+					    (void *)adev->irq.ih.ring,
+					    adev->irq.ih.rb_dma_addr);
 			adev->irq.ih.ring = NULL;
 		}
 	} else {


Patches currently in stable-queue which might be from alexander.deucher@amd.com are

queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch
queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch
queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch
queue-4.2/drm-radeon-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch
queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch
queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch
queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch
queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch
queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch