[PATCH resend 0/2] mips: c-r4k: detect secondary cache

[PATCH resend 0/2] mips: c-r4k: detect secondary cache

[Peter Mamonov]

These two patches implement secondary cache detection and report its 
configuration via cpuinfo command.

Peter Mamonov (2):
	[PATCH resend 1/2] mips: c-r4k: detect secondary cache
	[PATCH resend 2/2] mips: cpuinfo: report secondary cache

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[PATCH resend 1/2] mips: c-r4k: detect secondary cache

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/lib/c-r4k.c     | 31 +++++++++++++++++++++++++++++++
 arch/mips/lib/cpu-probe.c |  2 --
 2 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 01b8665..0a9dd0e 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -91,7 +91,38 @@ static void probe_pcache(void)
 	}
 }
 
+#define CONFIG_M	(1 << 31)
+#define CONFIG2_SS_OFFSET	8
+#define CONFIG2_SL_OFFSET	4
+#define CONFIG2_SA_OFFSET	0
+static void probe_scache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+	unsigned int config2, config1, config = read_c0_config();
+	unsigned int ss, sl, sa;
+
+	if ((config & CONFIG_M) == 0)
+		goto noscache;
+	config1 = read_c0_config1();
+	if ((config1 & CONFIG_M) == 0)
+		goto noscache;
+	config2 = read_c0_config2();
+	ss = 0xf & (config2 >> CONFIG2_SS_OFFSET);
+	sl = 0xf & (config2 >> CONFIG2_SL_OFFSET);
+	sa = 0xf & (config2 >> CONFIG2_SA_OFFSET);
+	if (sl == 0)
+		goto noscache;
+	c->scache.linesz = 1 << (sl + 1);
+	c->scache.sets = 64 << ss;
+	c->scache.ways = 1 + sa;
+	c->scache.waysize = c->scache.linesz * c->scache.sets;
+	return;
+noscache:
+	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
+}
+
 void r4k_cache_init(void)
 {
 	probe_pcache();
+	probe_scache();
 }
diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c
index 4622bcd..71dbaf6 100644
--- a/arch/mips/lib/cpu-probe.c
+++ b/arch/mips/lib/cpu-probe.c
@@ -75,8 +75,6 @@ static void decode_configs(struct cpuinfo_mips *c)
 	c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 	             MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 
-	c->scache.flags = MIPS_CACHE_NOT_PRESENT;
-
 	ok = decode_config0(c);			/* Read Config registers.  */
 	BUG_ON(!ok);				/* Arch spec violation!  */
 }
-- 
2.1.4


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[PATCH resend 2/2] mips: cpuinfo: report secondary cache configuration

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/lib/cpuinfo.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c
index 1b17169..fb02a4d 100644
--- a/arch/mips/lib/cpuinfo.c
+++ b/arch/mips/lib/cpuinfo.c
@@ -28,7 +28,7 @@ static char *way_string[] = { NULL, "direct mapped", "2-way",
 
 static int do_cpuinfo(int argc, char *argv[])
 {
-	unsigned int icache_size, dcache_size;
+	unsigned int icache_size, dcache_size, scache_size;
 	struct cpuinfo_mips *c = &current_cpu_data;
 
 	printk(KERN_INFO "CPU revision is: %08x (%s)\n",
@@ -48,6 +48,15 @@ static int do_cpuinfo(int argc, char *argv[])
 	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?
 			"cache aliases" : "no aliases",
 	       c->dcache.linesz);
+	if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
+		return 0;
+	scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
+	printk("Secondary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+	       scache_size >> 10, way_string[c->scache.ways],
+	       (c->scache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+	       (c->scache.flags & MIPS_CACHE_ALIASES) ?
+			"cache aliases" : "no aliases",
+	       c->scache.linesz);
 
 	return 0;
 }
-- 
2.1.4


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Re: [PATCH resend 0/2] mips: c-r4k: detect secondary cache

[Sascha Hauer]

On Mon, Nov 02, 2015 at 07:49:58PM +0300, Peter Mamonov wrote:
> These two patches implement secondary cache detection and report its 
> configuration via cpuinfo command.
> 
> Peter Mamonov (2):
> 	[PATCH resend 1/2] mips: c-r4k: detect secondary cache
> 	[PATCH resend 2/2] mips: cpuinfo: report secondary cache

Applied, thanks

Sascha


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