* [PATCH v2 1/2] xen/serial: Move any OMAP specific things to OMAP UART driver
2015-11-05 17:53 [PATCH v2 0/2] xen/serial: Return actual bytes stored in TX FIFO for OMAP Oleksandr Tyshchenko
@ 2015-11-05 17:53 ` Oleksandr Tyshchenko
2015-11-06 11:26 ` Jan Beulich
2015-11-05 17:53 ` [PATCH v2 2/2] xen/serial: Return actual bytes stored in TX FIFO for OMAP Oleksandr Tyshchenko
1 sibling, 1 reply; 6+ messages in thread
From: Oleksandr Tyshchenko @ 2015-11-05 17:53 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, tim, ian.campbell, stefano.stabellini
The 8250-uart.h contains extra serial register definitions
for the internal UARTs in TI OMAP SoCs which are used in
OMAP UART driver only.
In order to clean up code move these definitions to omap-uart.c.
Also rename some definitions to follow to the UART_OMAP* prefix.
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com>
CC: Ian Campbell <ian.campbell@citrix.com>
CC: Julien Grall <julien.grall@citrix.com>
CC: Stefano Stabellini <stefano.stabellini@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>
---
xen/drivers/char/omap-uart.c | 25 ++++++++++++++++++++++---
xen/include/xen/8250-uart.h | 24 ------------------------
2 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c
index 16d1454..1c89d5f 100644
--- a/xen/drivers/char/omap-uart.c
+++ b/xen/drivers/char/omap-uart.c
@@ -25,6 +25,25 @@
#define REG_SHIFT 2
+/* Register offsets */
+#define UART_OMAP_EFR 0x02 /* Enhanced feature register */
+#define UART_OMAP_MDR1 0x08 /* Mode definition register 1 */
+#define UART_OMAP_SCR 0x10 /* Supplementary control register */
+#define UART_OMAP_SYSC 0x15 /* System configuration register */
+
+/* Enhanced feature register */
+#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
+
+/* Mode definition register 1 */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
+/* Supplementary control register bitmasks */
+#define UART_OMAP_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+
+/* System configuration register */
+#define UART_OMAP_SYSC_DEF_CONF 0x0d /* autoidle mode, wakeup is enabled */
+
#define omap_read(uart, off) readl((uart)->regs + (off<<REG_SHIFT))
#define omap_write(uart, off, val) writel((val), (uart)->regs + (off<<REG_SHIFT))
@@ -146,7 +165,7 @@ static void fifo_setup(struct omap_uart *uart)
/*
* Load the new FIFO triggers and the new DMA mode bit.
*/
- omap_write(uart, UART_OMAP_SCR, OMAP_UART_SCR_RX_TRIG_GRANU1_MASK);
+ omap_write(uart, UART_OMAP_SCR, UART_OMAP_SCR_RX_TRIG_GRANU1_MASK);
/*
* Restore the UART_OMAP_EFR[4] value.
*/
@@ -196,8 +215,8 @@ static void __init omap_uart_init_preirq(struct serial_port *port)
omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
- /* setup iddle mode */
- omap_write(uart, UART_SYSC, OMAP_UART_SYSC_DEF_CONF);
+ /* setup idle mode */
+ omap_write(uart, UART_OMAP_SYSC, UART_OMAP_SYSC_DEF_CONF);
}
static void __init omap_uart_init_postirq(struct serial_port *port)
diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
index 304b9dd..c6b62c8 100644
--- a/xen/include/xen/8250-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -32,7 +32,6 @@
#define UART_MCR 0x04 /* Modem control */
#define UART_LSR 0x05 /* line status */
#define UART_MSR 0x06 /* Modem status */
-#define UART_SYSC 0x15 /* System configuration register */
#define UART_USR 0x1f /* Status register (DW) */
#define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */
#define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */
@@ -126,29 +125,6 @@
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
-/* Enhanced feature register */
-#define UART_OMAP_EFR 0x02
-
-#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
-
-/* Mode definition register 1 */
-#define UART_OMAP_MDR1 0x08
-
-/*
- * These are the definitions for the MDR1 register
- */
-#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
-#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
-
-/* Supplementary control register */
-#define UART_OMAP_SCR 0x10
-
-/* SCR register bitmasks */
-#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
-
-/* System configuration register */
-#define OMAP_UART_SYSC_DEF_CONF 0x0d /* autoidle mode, wakeup is enabled */
-
#endif /* __XEN_8250_UART_H__ */
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/2] xen/serial: Return actual bytes stored in TX FIFO for OMAP
2015-11-05 17:53 [PATCH v2 0/2] xen/serial: Return actual bytes stored in TX FIFO for OMAP Oleksandr Tyshchenko
2015-11-05 17:53 ` [PATCH v2 1/2] xen/serial: Move any OMAP specific things to OMAP UART driver Oleksandr Tyshchenko
@ 2015-11-05 17:53 ` Oleksandr Tyshchenko
1 sibling, 0 replies; 6+ messages in thread
From: Oleksandr Tyshchenko @ 2015-11-05 17:53 UTC (permalink / raw)
To: xen-devel; +Cc: julien.grall, tim, ian.campbell, stefano.stabellini
This is intended to decrease a time spending in transmitter
while waiting for the free space in TX FIFO.
And as result to reduce the impact of hvc on the entire system
running on OMAP5/DRA7XX based platforms.
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com>
CC: Ian Campbell <ian.campbell@citrix.com>
CC: Julien Grall <julien.grall@citrix.com>
CC: Stefano Stabellini <stefano.stabellini@citrix.com>
Cc: Jan Beulich <jbeulich@suse.com>
---
xen/drivers/char/omap-uart.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c
index 1c89d5f..28b6d0d 100644
--- a/xen/drivers/char/omap-uart.c
+++ b/xen/drivers/char/omap-uart.c
@@ -29,7 +29,9 @@
#define UART_OMAP_EFR 0x02 /* Enhanced feature register */
#define UART_OMAP_MDR1 0x08 /* Mode definition register 1 */
#define UART_OMAP_SCR 0x10 /* Supplementary control register */
+#define UART_OMAP_SSR 0x11 /* Supplementary status register */
#define UART_OMAP_SYSC 0x15 /* System configuration register */
+#define UART_OMAP_TXFIFO_LVL 0x1A /* TX FIFO level register */
/* Enhanced feature register */
#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
@@ -41,6 +43,9 @@
/* Supplementary control register bitmasks */
#define UART_OMAP_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+/* Supplementary status register bitmasks */
+#define UART_OMAP_SSR_TX_FIFO_FULL_MASK (1 << 0)
+
/* System configuration register */
#define UART_OMAP_SYSC_DEF_CONF 0x0d /* autoidle mode, wakeup is enabled */
@@ -252,11 +257,20 @@ static int omap_uart_tx_ready(struct serial_port *port)
{
struct omap_uart *uart = port->uart;
uint32_t reg;
+ uint8_t cnt;
reg = omap_read(uart, UART_IER);
omap_write(uart, UART_IER, reg | UART_IER_ETHREI);
- return omap_read(uart, UART_LSR) & UART_LSR_THRE ? uart->fifo_size : 0;
+ /* Check for empty space in TX FIFO */
+ if ( omap_read(uart, UART_OMAP_SSR) & UART_OMAP_SSR_TX_FIFO_FULL_MASK )
+ return 0;
+
+ /* Check number of data bytes stored in TX FIFO */
+ cnt = omap_read(uart, UART_OMAP_TXFIFO_LVL);
+ ASSERT( cnt >= 0 && cnt <= uart->fifo_size );
+
+ return (uart->fifo_size - cnt);
}
static void omap_uart_putc(struct serial_port *port, char c)
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread