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From: Prem Mallappa <pmallapp-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
	will.deacon-5wv7dgnIgG8@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: jchandra-dY08KVG/lbpWk0Htik3J/w@public.gmane.org,
	Prem Mallappa <pmallapp-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Subject: [PATCH] IOMMU: arm-smmu-v3: fix broken S2PS and AARCH64 in Broadcom Vulcan
Date: Mon, 14 Dec 2015 22:01:27 +0530	[thread overview]
Message-ID: <1450110687-32207-1-git-send-email-pmallapp@broadcom.com> (raw)

Vulcan SMMUv3 looks for AARCH64 and S2PS inroder to validate the STE entry,
which is a overkill, but when proper encoding not found; the SMMU stops
processing PCIe read/write requests. Giving the h/w what it wants.

Signed-off-by: Prem Mallappa <pmallapp-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
 drivers/iommu/arm-smmu-v3.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index d4af50d..dfda564 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -260,6 +260,7 @@
 #define STRTAB_STE_2_S2VMID_MASK	0xffffUL
 #define STRTAB_STE_2_VTCR_SHIFT		32
 #define STRTAB_STE_2_VTCR_MASK		0x7ffffUL
+#define STRTAB_STE_2_S2PS_SHIFT        48
 #define STRTAB_STE_2_S2AA64		(1UL << 51)
 #define STRTAB_STE_2_S2ENDI		(1UL << 52)
 #define STRTAB_STE_2_S2PTW		(1UL << 54)
@@ -577,6 +578,7 @@ struct arm_smmu_device {
 	u32				features;
 
 #define ARM_SMMU_OPT_SKIP_PREFETCH	(1 << 0)
+#define ARM_SMMU_OPT_BROKEN_STE_VALID	(1 << 1)
 	u32				options;
 
 	struct arm_smmu_cmdq		cmdq;
@@ -641,6 +643,7 @@ struct arm_smmu_option_prop {
 
 static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
+	{ ARM_SMMU_OPT_BROKEN_STE_VALID, "broadcom,broken-ste-valid-check" },
 	{ 0, NULL},
 };
 
@@ -1046,6 +1049,15 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
 				      : STRTAB_STE_0_CFG_BYPASS;
 		dst[0] = cpu_to_le64(val);
 		dst[2] = 0; /* Nuke the VMID */
+
+		if (smmu && (smmu->options & ARM_SMMU_OPT_BROKEN_STE_VALID)) {
+#define SMMU_STE_OAS_44_BITS 0x4UL
+			WARN_ON(smmu->oas != 44);
+			dst[1] = STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT;
+			dst[2] |= cpu_to_le64((SMMU_STE_OAS_44_BITS << STRTAB_STE_2_S2PS_SHIFT) |
+					STRTAB_STE_2_S2AA64);
+		}
+
 		if (ste_live)
 			arm_smmu_sync_ste_for_sid(smmu, sid);
 		return;
-- 
2.6.0

WARNING: multiple messages have this Message-ID (diff)
From: pmallapp@broadcom.com (Prem Mallappa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] IOMMU: arm-smmu-v3: fix broken S2PS and AARCH64 in Broadcom Vulcan
Date: Mon, 14 Dec 2015 22:01:27 +0530	[thread overview]
Message-ID: <1450110687-32207-1-git-send-email-pmallapp@broadcom.com> (raw)

Vulcan SMMUv3 looks for AARCH64 and S2PS inroder to validate the STE entry,
which is a overkill, but when proper encoding not found; the SMMU stops
processing PCIe read/write requests. Giving the h/w what it wants.

Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
---
 drivers/iommu/arm-smmu-v3.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index d4af50d..dfda564 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -260,6 +260,7 @@
 #define STRTAB_STE_2_S2VMID_MASK	0xffffUL
 #define STRTAB_STE_2_VTCR_SHIFT		32
 #define STRTAB_STE_2_VTCR_MASK		0x7ffffUL
+#define STRTAB_STE_2_S2PS_SHIFT        48
 #define STRTAB_STE_2_S2AA64		(1UL << 51)
 #define STRTAB_STE_2_S2ENDI		(1UL << 52)
 #define STRTAB_STE_2_S2PTW		(1UL << 54)
@@ -577,6 +578,7 @@ struct arm_smmu_device {
 	u32				features;
 
 #define ARM_SMMU_OPT_SKIP_PREFETCH	(1 << 0)
+#define ARM_SMMU_OPT_BROKEN_STE_VALID	(1 << 1)
 	u32				options;
 
 	struct arm_smmu_cmdq		cmdq;
@@ -641,6 +643,7 @@ struct arm_smmu_option_prop {
 
 static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
+	{ ARM_SMMU_OPT_BROKEN_STE_VALID, "broadcom,broken-ste-valid-check" },
 	{ 0, NULL},
 };
 
@@ -1046,6 +1049,15 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
 				      : STRTAB_STE_0_CFG_BYPASS;
 		dst[0] = cpu_to_le64(val);
 		dst[2] = 0; /* Nuke the VMID */
+
+		if (smmu && (smmu->options & ARM_SMMU_OPT_BROKEN_STE_VALID)) {
+#define SMMU_STE_OAS_44_BITS 0x4UL
+			WARN_ON(smmu->oas != 44);
+			dst[1] = STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT;
+			dst[2] |= cpu_to_le64((SMMU_STE_OAS_44_BITS << STRTAB_STE_2_S2PS_SHIFT) |
+					STRTAB_STE_2_S2AA64);
+		}
+
 		if (ste_live)
 			arm_smmu_sync_ste_for_sid(smmu, sid);
 		return;
-- 
2.6.0

             reply	other threads:[~2015-12-14 16:31 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-14 16:31 Prem Mallappa [this message]
2015-12-14 16:31 ` [PATCH] IOMMU: arm-smmu-v3: fix broken S2PS and AARCH64 in Broadcom Vulcan Prem Mallappa
     [not found] ` <1450110687-32207-1-git-send-email-pmallapp-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2015-12-15 13:40   ` Will Deacon
2015-12-15 13:40     ` Will Deacon
     [not found]     ` <20151215134010.GH9452-5wv7dgnIgG8@public.gmane.org>
2015-12-15 15:48       ` Will Deacon
2015-12-15 15:48         ` Will Deacon
2015-12-16  4:37       ` Prem (Premachandra) Mallappa
2015-12-16  4:37         ` Prem (Premachandra) Mallappa
     [not found]         ` <CC0BC9CB4553B146B290EC1D4DC5C35901094BCE-HXj2mutaA2rOzKo2G4nwXJr/X4hKkxxPpWgKQ6/u3Fg@public.gmane.org>
2015-12-16 10:17           ` Will Deacon
2015-12-16 10:17             ` Will Deacon
     [not found]             ` <20151216101735.GB4308-5wv7dgnIgG8@public.gmane.org>
2015-12-16 10:49               ` Prem (Premachandra) Mallappa
2015-12-16 10:49                 ` Prem (Premachandra) Mallappa

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