From: "Lluís Vilanova" <vilanova@ac.upc.edu>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Guan Xuetao <gxt@mprc.pku.edu.cn>,
Eduardo Habkost <ehabkost@redhat.com>, Jia Liu <proljc@gmail.com>,
Anthony Green <green@moxielogic.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Alexander Graf <agraf@suse.de>, Blue Swirl <blauwirbel@gmail.com>,
Max Filippov <jcmvbkbc@gmail.com>,
Michael Walle <michael@walle.cc>,
"open list:ARM" <qemu-arm@nongnu.org>,
"open list:PowerPC" <qemu-ppc@nongnu.org>,
Stefan Hajnoczi <stefanha@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Leon Alrae <leon.alrae@imgtec.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-arm] [PATCH 1/5] exec: [tcg] Track which vCPU is performing translation and execution
Date: Tue, 23 Feb 2016 19:22:13 +0100 [thread overview]
Message-ID: <145625173293.12025.6340664976132573147.stgit@localhost> (raw)
In-Reply-To: <145625172744.12025.2350972792125742783.stgit@localhost>
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.
The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-alpha/translate.c | 1 +
target-arm/translate.c | 1 +
target-cris/translate.c | 1 +
target-cris/translate_v10.c | 1 +
target-i386/translate.c | 1 +
target-lm32/translate.c | 1 +
target-m68k/translate.c | 1 +
target-microblaze/translate.c | 1 +
target-mips/translate.c | 1 +
target-moxie/translate.c | 1 +
target-openrisc/translate.c | 1 +
target-ppc/translate.c | 1 +
target-s390x/translate.c | 1 +
target-sh4/translate.c | 1 +
target-sparc/translate.c | 1 +
target-tilegx/translate.c | 1 +
target-tricore/translate.c | 1 +
target-unicore32/translate.c | 1 +
target-xtensa/translate.c | 1 +
tcg/tcg.h | 4 ++++
translate-all.c | 2 ++
21 files changed, 25 insertions(+)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 7b798b0..aebe303 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -150,6 +150,7 @@ void alpha_translate_init(void)
done_init = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e69145d..5f8ea6b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -84,6 +84,7 @@ void arm_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 2a283e0..8d8e699 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3364,6 +3364,7 @@ void cris_initialize_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 7607ead..f2e9768 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1250,6 +1250,7 @@ void cris_initialize_crisv10_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9171929..ca2854d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8075,6 +8075,7 @@ void tcg_x86_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 3877993..e373d87 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1191,6 +1191,7 @@ void lm32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 085cb6a..d325c72 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -77,6 +77,7 @@ void m68k_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 296c4d7..bc7bcf9 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1869,6 +1869,7 @@ void mb_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 658926d..38969cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19829,6 +19829,7 @@ void mips_tcg_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index bc860a5..fccc011 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -106,6 +106,7 @@ void moxie_translate_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index d25324e..ae1e73a 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -78,6 +78,7 @@ void openrisc_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
env_flags = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ecc85f0..56f4212 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -87,6 +87,7 @@ void ppc_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 82e1165..db02983 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -168,6 +168,7 @@ void s390x_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index e35d175..2590760 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -100,6 +100,7 @@ void sh4_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 536c4b5..5e893d6 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5353,6 +5353,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
inited = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
"regwptr");
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 7073aba..b3de5ae 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2442,6 +2442,7 @@ void tilegx_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a70fdf7..49ac4a6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8368,6 +8368,7 @@ void tricore_tcg_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 1dd086d..e9efe32 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -69,6 +69,7 @@ void uc32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index fd03603..4efa1af 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -218,6 +218,7 @@ void xtensa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 83da5fb..73d9069 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -566,6 +566,10 @@ struct TCGContext {
TBContext tb_ctx;
+ /* Track which vCPU triggers events */
+ CPUState *cpu; /* *_trans */
+ TCGv_env tcg_env; /* *_exec */
+
/* The TCGBackendData structure is private to tcg-target.c. */
struct TCGBackendData *be;
diff --git a/translate-all.c b/translate-all.c
index e9f409b..c3de346 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1091,6 +1091,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
ti = profile_getclock();
#endif
+ tcg_ctx.cpu = ENV_GET_CPU(env);
+
tcg_func_start(&tcg_ctx);
gen_intermediate_code(env, tb);
WARNING: multiple messages have this Message-ID (diff)
From: "Lluís Vilanova" <vilanova@ac.upc.edu>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Guan Xuetao <gxt@mprc.pku.edu.cn>,
Eduardo Habkost <ehabkost@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Jia Liu <proljc@gmail.com>, Anthony Green <green@moxielogic.com>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Alexander Graf <agraf@suse.de>, Blue Swirl <blauwirbel@gmail.com>,
Max Filippov <jcmvbkbc@gmail.com>,
Michael Walle <michael@walle.cc>,
"open list:ARM" <qemu-arm@nongnu.org>,
"open list:PowerPC" <qemu-ppc@nongnu.org>,
Stefan Hajnoczi <stefanha@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Leon Alrae <leon.alrae@imgtec.com>,
Aurelien Jarno <aurelien@aurel32.net>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 1/5] exec: [tcg] Track which vCPU is performing translation and execution
Date: Tue, 23 Feb 2016 19:22:13 +0100 [thread overview]
Message-ID: <145625173293.12025.6340664976132573147.stgit@localhost> (raw)
In-Reply-To: <145625172744.12025.2350972792125742783.stgit@localhost>
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.
The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-alpha/translate.c | 1 +
target-arm/translate.c | 1 +
target-cris/translate.c | 1 +
target-cris/translate_v10.c | 1 +
target-i386/translate.c | 1 +
target-lm32/translate.c | 1 +
target-m68k/translate.c | 1 +
target-microblaze/translate.c | 1 +
target-mips/translate.c | 1 +
target-moxie/translate.c | 1 +
target-openrisc/translate.c | 1 +
target-ppc/translate.c | 1 +
target-s390x/translate.c | 1 +
target-sh4/translate.c | 1 +
target-sparc/translate.c | 1 +
target-tilegx/translate.c | 1 +
target-tricore/translate.c | 1 +
target-unicore32/translate.c | 1 +
target-xtensa/translate.c | 1 +
tcg/tcg.h | 4 ++++
translate-all.c | 2 ++
21 files changed, 25 insertions(+)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 7b798b0..aebe303 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -150,6 +150,7 @@ void alpha_translate_init(void)
done_init = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e69145d..5f8ea6b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -84,6 +84,7 @@ void arm_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 2a283e0..8d8e699 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3364,6 +3364,7 @@ void cris_initialize_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 7607ead..f2e9768 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1250,6 +1250,7 @@ void cris_initialize_crisv10_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9171929..ca2854d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8075,6 +8075,7 @@ void tcg_x86_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 3877993..e373d87 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1191,6 +1191,7 @@ void lm32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 085cb6a..d325c72 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -77,6 +77,7 @@ void m68k_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 296c4d7..bc7bcf9 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1869,6 +1869,7 @@ void mb_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 658926d..38969cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19829,6 +19829,7 @@ void mips_tcg_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index bc860a5..fccc011 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -106,6 +106,7 @@ void moxie_translate_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index d25324e..ae1e73a 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -78,6 +78,7 @@ void openrisc_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
env_flags = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ecc85f0..56f4212 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -87,6 +87,7 @@ void ppc_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 82e1165..db02983 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -168,6 +168,7 @@ void s390x_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index e35d175..2590760 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -100,6 +100,7 @@ void sh4_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 536c4b5..5e893d6 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5353,6 +5353,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
inited = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
"regwptr");
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 7073aba..b3de5ae 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2442,6 +2442,7 @@ void tilegx_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a70fdf7..49ac4a6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8368,6 +8368,7 @@ void tricore_tcg_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 1dd086d..e9efe32 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -69,6 +69,7 @@ void uc32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index fd03603..4efa1af 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -218,6 +218,7 @@ void xtensa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 83da5fb..73d9069 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -566,6 +566,10 @@ struct TCGContext {
TBContext tb_ctx;
+ /* Track which vCPU triggers events */
+ CPUState *cpu; /* *_trans */
+ TCGv_env tcg_env; /* *_exec */
+
/* The TCGBackendData structure is private to tcg-target.c. */
struct TCGBackendData *be;
diff --git a/translate-all.c b/translate-all.c
index e9f409b..c3de346 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1091,6 +1091,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
ti = profile_getclock();
#endif
+ tcg_ctx.cpu = ENV_GET_CPU(env);
+
tcg_func_start(&tcg_ctx);
gen_intermediate_code(env, tb);
next prev parent reply other threads:[~2016-02-23 18:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-23 18:22 [Qemu-devel] [PATCH 0/5] trace: Add events for vCPU memory accesses Lluís Vilanova
2016-02-23 18:22 ` Lluís Vilanova [this message]
2016-02-23 18:22 ` [Qemu-devel] [PATCH 1/5] exec: [tcg] Track which vCPU is performing translation and execution Lluís Vilanova
2016-03-16 15:01 ` [Qemu-arm] " Peter Maydell
2016-03-16 15:01 ` [Qemu-devel] " Peter Maydell
2016-02-23 18:22 ` [Qemu-devel] [PATCH 2/5] trace: [all] Add "guest_vmem" event Lluís Vilanova
2016-03-16 15:01 ` Peter Maydell
2016-03-17 19:22 ` Lluís Vilanova
2016-03-17 20:18 ` Richard Henderson
2016-03-17 20:25 ` Peter Maydell
2016-03-18 18:50 ` Lluís Vilanova
2016-03-19 13:59 ` Peter Maydell
2016-03-20 18:09 ` Lluís Vilanova
2016-03-20 19:59 ` Peter Maydell
2016-03-21 16:51 ` Lluís Vilanova
2016-02-23 18:22 ` [Qemu-devel] [PATCH 3/5] user: Refactor lock_user body into do_lock_user Lluís Vilanova
2016-02-23 18:22 ` [Qemu-devel] [PATCH 4/5] user: Set current vCPU during syscall execution Lluís Vilanova
2016-02-23 18:22 ` [Qemu-devel] [PATCH 5/5] trace: [all] Add "guest_vmem_user_syscall" event Lluís Vilanova
2016-03-02 10:55 ` [Qemu-devel] [PATCH 0/5] trace: Add events for vCPU memory accesses Stefan Hajnoczi
2016-03-16 15:10 ` Peter Maydell
2016-03-22 12:55 ` Stefan Hajnoczi
2016-03-22 14:02 ` Lluís Vilanova
2016-03-22 14:47 ` Peter Maydell
2016-03-22 19:23 ` Lluís Vilanova
2016-03-22 20:23 ` Peter Maydell
2016-03-23 14:08 ` Lluís Vilanova
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