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From: Imre Deak <imre.deak@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: Re: [PATCH 4/6] drm/i915: Read out hrawclk from CCK on vlv/chv
Date: Thu, 03 Mar 2016 20:13:48 +0200	[thread overview]
Message-ID: <1457028828.16462.1.camel@intel.com> (raw)
In-Reply-To: <1456932138-14004-5-git-send-email-ville.syrjala@linux.intel.com>

On Wed, 2016-03-02 at 17:22 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we assume that hrawclk is 200MHz on VLV/CHV. That should
> be true always, but just to avoid such asumptions we can read out the
> actual frequency from CCK.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Matches both the VLV and CHV clock spec, so:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 1 +
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 71abf5725495..c4606c7ad8d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -786,6 +786,7 @@ enum skl_disp_power_wells {
>  #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
>  #define CCK_CZ_CLOCK_CONTROL			0x62
>  #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
> +#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
>  #define  CCK_TRUNK_FORCE_ON			(1 << 17)
>  #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
>  #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 330528c1fb28..f5a757bec3f7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -178,7 +178,8 @@ intel_pch_rawclk(struct drm_i915_private
> *dev_priv)
>  static int
>  intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
>  {
> -	return 200000;
> +	return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
> +				      CCK_DISPLAY_REF_CLOCK_CONTROL)
> ;
>  }
>  
>  static int
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  parent reply	other threads:[~2016-03-03 18:13 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-02 15:22 [PATCH v2 drm/i915: rawclk/cdclk stuff (v2) ville.syrjala
2016-03-02 15:22 ` [PATCH v2 1/6] drm/i915: Store rawclk_freq in dev_priv ville.syrjala
2016-03-03  8:47   ` Jani Nikula
2016-03-03 10:59     ` Ville Syrjälä
2016-03-02 15:22 ` [PATCH 2/6] drm/i915: Rename s/i9xx/g4x/ in DP code ville.syrjala
2016-03-02 15:22 ` [PATCH v2 3/6] drm/i915: Use g4x_get_aux_clock_divider() for VLV/CHV ville.syrjala
2016-03-02 15:22 ` [PATCH 4/6] drm/i915: Read out hrawclk from CCK on vlv/chv ville.syrjala
2016-03-03  8:51   ` Jani Nikula
2016-03-03 11:04     ` Ville Syrjälä
2016-03-03 18:13   ` Imre Deak [this message]
2016-03-02 15:22 ` [PATCH 5/6] drm/i915: Clean up .get_aux_clock_divider() functions ville.syrjala
2016-03-02 15:22 ` [PATCH 6/6] drm/i915: Use DIV_ROUND_CLOSEST for PWM calculations ville.syrjala
2016-03-03  8:25   ` Jani Nikula
2016-03-03 10:54     ` Ville Syrjälä
2016-03-02 16:55 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915: Store rawclk_freq in dev_priv Patchwork
2016-03-02 17:27   ` Ville Syrjälä
2016-03-04 12:56 ` [PATCH v2 drm/i915: rawclk/cdclk stuff (v2) Ville Syrjälä

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