[PATCH v3 00/19] Split driver init step to phases

[PATCH v3 00/19] Split driver init step to phases

[Imre Deak]

This is v3 of [1]. It includes now the fault injection patches Chris
requested and addresses comments from Daniel and Joonas. Since IGT has
by now an updated drv_module_reload_basic too using load failure
injection, CI hopefully catches any problems introduced by this
patchset.

CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Jani Nikula <jani.nikula@intel.com>
CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>

[1]
https://lists.freedesktop.org/archives/intel-gfx/2016-March/089596.html

Imre Deak (19):
  Fix MCHBAR cleanup on the driver init error path
  drm/i915: Move load time PCH detect, DPIO, power domain SW init
    earlier
  drm/i915: Move load time IRQ SW init earlier
  drm/i915: Move load time init of display/audio hooks earlier
  drm/i915: Move load time init of clock gating hooks earlier
  drm/i915: Move load time runtime device info init earlier
  drm/i915: Move load time gem_load_init earlier
  drm/i915: Move load time runtime PM get later
  drm/i915: Move load time shrinker registration later
  drm/i915: Move load time audio component registration earlier
  drm/i915: Move unload time display power domain uninit later
  drm/i915: Move unload time GTT, MSI IRQ cleanup later
  drm/i915: Move unload time opregion unregistration earlier
  drm/i915: Split out load time early initialization
  drm/i915: Split out load time MMIO initialization
  drm/i915: Split out load time HW initialization
  drm/i915: Split out load time interface registration
  drm/i915: Fix power domain HW state cleanup on error path
  drm/i915: Add fault injection support

 drivers/gpu/drm/i915/i915_dma.c      | 399 ++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/i915_drv.h      |   5 +
 drivers/gpu/drm/i915/i915_gem.c      |  34 +--
 drivers/gpu/drm/i915/i915_irq.c      |   2 -
 drivers/gpu/drm/i915/i915_params.c   |   5 +
 drivers/gpu/drm/i915/i915_params.h   |   1 +
 drivers/gpu/drm/i915/intel_audio.c   |  16 +-
 drivers/gpu/drm/i915/intel_display.c |  82 ++++---
 drivers/gpu/drm/i915/intel_drv.h     |   4 +-
 drivers/gpu/drm/i915/intel_pm.c      |  91 +++++---
 10 files changed, 409 insertions(+), 230 deletions(-)

-- 
2.5.0

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[PATCH v3 01/19] Fix MCHBAR cleanup on the driver init error path

[Imre Deak]

MCHBAR is cleaned up in i915_mmio_cleanup(), so the separate call in
i915_driver_load() is incorrect.

CC: David Weinehall <david.weinehall@intel.com>
Fixes: ad5c3d3ffbb2 ("drm/i915: Move MCHBAR setup earlier during init")
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4aa3db6..fbb9815 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1175,7 +1175,6 @@ out_gem_unload:
 	if (dev->pdev->msi_enabled)
 		pci_disable_msi(dev->pdev);
 
-	intel_teardown_mchbar(dev);
 	pm_qos_remove_request(&dev_priv->pm_qos);
 	arch_phys_wc_del(dev_priv->gtt.mtrr);
 	io_mapping_free(dev_priv->gtt.mappable);
-- 
2.5.0

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[PATCH v3 02/19] drm/i915: Move load time PCH detect, DPIO, power domain SW init earlier

[Imre Deak]

These are all SW only init steps not accessing the device and they only
need the platform identification macros to work, which are already
available earlier, so move these init steps earlier.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index fbb9815..a7bda8a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1020,7 +1020,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (ret < 0)
 		goto out_free_priv;
 
+	/* This must be called before any calls to HAS_PCH_* */
+	intel_detect_pch(dev);
+
 	intel_pm_setup(dev);
+	intel_init_dpio(dev_priv);
+	intel_power_domains_init(dev_priv);
 
 	intel_runtime_pm_get(dev_priv);
 
@@ -1045,9 +1050,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (ret < 0)
 		goto put_bridge;
 
-	/* This must be called before any calls to HAS_PCH_* */
-	intel_detect_pch(dev);
-
 	intel_uncore_init(dev);
 
 	ret = i915_gem_gtt_init(dev);
@@ -1124,16 +1126,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_device_info_runtime_init(dev);
 
-	intel_init_dpio(dev_priv);
-
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
 			goto out_gem_unload;
 	}
 
-	intel_power_domains_init(dev_priv);
-
 	ret = i915_load_modeset_init(dev);
 	if (ret < 0) {
 		DRM_ERROR("failed to init modeset\n");
-- 
2.5.0

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[PATCH v3 03/19] drm/i915: Move load time IRQ SW init earlier

[Imre Deak]

Most of the IRQ init is setting up hooks so move that part earlier.
Leave the pm_qos_add_request() call in place.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 5 ++++-
 drivers/gpu/drm/i915/i915_irq.c | 2 --
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a7bda8a..4cf7bd4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1026,6 +1026,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_pm_setup(dev);
 	intel_init_dpio(dev_priv);
 	intel_power_domains_init(dev_priv);
+	intel_irq_init(dev_priv);
 
 	intel_runtime_pm_get(dev_priv);
 
@@ -1100,7 +1101,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 					      aperture_size);
 
-	intel_irq_init(dev_priv);
+	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
+			   PM_QOS_DEFAULT_VALUE);
+
 	intel_uncore_sanitize(dev);
 
 	intel_opregion_setup(dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 53e5104..8c7f730 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4564,8 +4564,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
 			  i915_hangcheck_elapsed);
 
-	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
-
 	if (IS_GEN2(dev_priv)) {
 		dev->max_vblank_count = 0;
 		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
-- 
2.5.0

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[PATCH v3 04/19] drm/i915: Move load time init of display/audio hooks earlier

[Imre Deak]

All of this is SW only initialization so we can move them earlier. Move
the mutex init where the rest of the locks are inited. While at it also
convert dev to dev_priv.

v2:
- use the term hook instead of callback for these functions (Jani)

CC: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c      |  3 ++
 drivers/gpu/drm/i915/intel_audio.c   | 16 +++----
 drivers/gpu/drm/i915/intel_display.c | 82 +++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_drv.h     |  3 +-
 4 files changed, 51 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4cf7bd4..44f15de 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1015,6 +1015,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	mutex_init(&dev_priv->modeset_restore_lock);
 	mutex_init(&dev_priv->av_mutex);
 	mutex_init(&dev_priv->wm.wm_mutex);
+	mutex_init(&dev_priv->pps_mutex);
 
 	ret = i915_workqueues_init(dev_priv);
 	if (ret < 0)
@@ -1027,6 +1028,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_init_dpio(dev_priv);
 	intel_power_domains_init(dev_priv);
 	intel_irq_init(dev_priv);
+	intel_init_display_hooks(dev_priv);
+	intel_init_audio_hooks(dev_priv);
 
 	intel_runtime_pm_get(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 30f9214..fdc8b2a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -564,23 +564,21 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 }
 
 /**
- * intel_init_audio - Set up chip specific audio functions
- * @dev: drm device
+ * intel_init_audio_hooks - Set up chip specific audio hooks
+ * @dev_priv: device private
  */
-void intel_init_audio(struct drm_device *dev)
+void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (IS_G4X(dev)) {
+	if (IS_G4X(dev_priv)) {
 		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
-	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
-	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
+	} else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
 		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ce55f0b..f623342 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14827,23 +14827,24 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.atomic_state_clear = intel_atomic_state_clear,
 };
 
-/* Set up chip specific display functions */
-static void intel_init_display(struct drm_device *dev)
+/**
+ * intel_init_display_hooks - initialize the display modesetting hooks
+ * @dev_priv: device private
+ */
+void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
+	if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
 		dev_priv->display.find_dpll = g4x_find_best_dpll;
-	else if (IS_CHERRYVIEW(dev))
+	else if (IS_CHERRYVIEW(dev_priv))
 		dev_priv->display.find_dpll = chv_find_best_dpll;
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev_priv))
 		dev_priv->display.find_dpll = vlv_find_best_dpll;
-	else if (IS_PINEVIEW(dev))
+	else if (IS_PINEVIEW(dev_priv))
 		dev_priv->display.find_dpll = pnv_find_best_dpll;
 	else
 		dev_priv->display.find_dpll = i9xx_find_best_dpll;
 
-	if (INTEL_INFO(dev)->gen >= 9) {
+	if (INTEL_INFO(dev_priv)->gen >= 9) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			skylake_get_initial_plane_config;
@@ -14851,7 +14852,7 @@ static void intel_init_display(struct drm_device *dev)
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
-	} else if (HAS_DDI(dev)) {
+	} else if (HAS_DDI(dev_priv)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
@@ -14859,7 +14860,7 @@ static void intel_init_display(struct drm_device *dev)
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
@@ -14867,7 +14868,7 @@ static void intel_init_display(struct drm_device *dev)
 			ironlake_crtc_compute_clock;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
-	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
@@ -14884,89 +14885,89 @@ static void intel_init_display(struct drm_device *dev)
 	}
 
 	/* Returns the core display clock speed */
-	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			skylake_get_display_clock_speed;
-	else if (IS_BROXTON(dev))
+	else if (IS_BROXTON(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			broxton_get_display_clock_speed;
-	else if (IS_BROADWELL(dev))
+	else if (IS_BROADWELL(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			broadwell_get_display_clock_speed;
-	else if (IS_HASWELL(dev))
+	else if (IS_HASWELL(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			haswell_get_display_clock_speed;
-	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
-	else if (IS_GEN5(dev))
+	else if (IS_GEN5(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			ilk_get_display_clock_speed;
-	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
-		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+	else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
+		 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
-	else if (IS_GM45(dev))
+	else if (IS_GM45(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			gm45_get_display_clock_speed;
-	else if (IS_CRESTLINE(dev))
+	else if (IS_CRESTLINE(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i965gm_get_display_clock_speed;
-	else if (IS_PINEVIEW(dev))
+	else if (IS_PINEVIEW(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			pnv_get_display_clock_speed;
-	else if (IS_G33(dev) || IS_G4X(dev))
+	else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			g33_get_display_clock_speed;
-	else if (IS_I915G(dev))
+	else if (IS_I915G(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i915_get_display_clock_speed;
-	else if (IS_I945GM(dev) || IS_845G(dev))
+	else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i9xx_misc_get_display_clock_speed;
-	else if (IS_I915GM(dev))
+	else if (IS_I915GM(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i915gm_get_display_clock_speed;
-	else if (IS_I865G(dev))
+	else if (IS_I865G(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i865_get_display_clock_speed;
-	else if (IS_I85X(dev))
+	else if (IS_I85X(dev_priv))
 		dev_priv->display.get_display_clock_speed =
 			i85x_get_display_clock_speed;
 	else { /* 830 */
-		WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
+		WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 	}
 
-	if (IS_GEN5(dev)) {
+	if (IS_GEN5(dev_priv)) {
 		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
-	} else if (IS_GEN6(dev)) {
+	} else if (IS_GEN6(dev_priv)) {
 		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
-	} else if (IS_IVYBRIDGE(dev)) {
+	} else if (IS_IVYBRIDGE(dev_priv)) {
 		/* FIXME: detect B0+ stepping and use auto training */
 		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
-	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
-		if (IS_BROADWELL(dev)) {
+		if (IS_BROADWELL(dev_priv)) {
 			dev_priv->display.modeset_commit_cdclk =
 				broadwell_modeset_commit_cdclk;
 			dev_priv->display.modeset_calc_cdclk =
 				broadwell_modeset_calc_cdclk;
 		}
-	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.modeset_commit_cdclk =
 			valleyview_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			valleyview_modeset_calc_cdclk;
-	} else if (IS_BROXTON(dev)) {
+	} else if (IS_BROXTON(dev_priv)) {
 		dev_priv->display.modeset_commit_cdclk =
 			broxton_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			broxton_modeset_calc_cdclk;
 	}
 
-	switch (INTEL_INFO(dev)->gen) {
+	switch (INTEL_INFO(dev_priv)->gen) {
 	case 2:
 		dev_priv->display.queue_flip = intel_gen2_queue_flip;
 		break;
@@ -14993,8 +14994,6 @@ static void intel_init_display(struct drm_device *dev)
 		/* Default just returns -ENODEV to indicate unsupported */
 		dev_priv->display.queue_flip = intel_default_queue_flip;
 	}
-
-	mutex_init(&dev_priv->pps_mutex);
 }
 
 /*
@@ -15321,9 +15320,6 @@ void intel_modeset_init(struct drm_device *dev)
 		}
 	}
 
-	intel_init_display(dev);
-	intel_init_audio(dev);
-
 	if (IS_GEN2(dev)) {
 		dev->mode_config.max_width = 2048;
 		dev->mode_config.max_height = 2048;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02b3d22..d0f05a8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1109,7 +1109,7 @@ u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
 			      uint64_t fb_modifier, uint32_t pixel_format);
 
 /* intel_audio.c */
-void intel_init_audio(struct drm_device *dev);
+void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
 void intel_audio_codec_enable(struct intel_encoder *encoder);
 void intel_audio_codec_disable(struct intel_encoder *encoder);
 void i915_audio_component_init(struct drm_i915_private *dev_priv);
@@ -1117,6 +1117,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 
 /* intel_display.c */
 extern const struct drm_plane_funcs intel_plane_funcs;
+void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
-- 
2.5.0

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[PATCH v3 05/19] drm/i915: Move load time init of clock gating hooks earlier

[Imre Deak]

Split out the part initing the clock gating hooks and move it earlier.
Add a new NOP hook for platforms without the need to apply clockgating
or workaround settings, so that the hook can be called unconditionally.
Also add a WARN for future platforms that forget to add a hook.

The rest of the hooks in intel_init_pm() should be inited in the same
way, but atm some of the hooks are set only conditionally, so before
doing this we need to make the setup unconditional and use instead some
flags.

v2:
- add a NOP hook and WARN if no hook is set for the platform (Chris)
- use the term hook instead of callback for these functions (Jani)
v3:
- remove the GEN4() check it's already covered by earlier platform
  checks (Chris)

CC: Jani Nikula <jani.nikula@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 91 ++++++++++++++++++++++++----------------
 3 files changed, 58 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44f15de..60e8fe6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1029,6 +1029,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_power_domains_init(dev_priv);
 	intel_irq_init(dev_priv);
 	intel_init_display_hooks(dev_priv);
+	intel_init_clock_gating_hooks(dev_priv);
 	intel_init_audio_hooks(dev_priv);
 
 	intel_runtime_pm_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d0f05a8..7a642ae 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1587,6 +1587,7 @@ void intel_suspend_hw(struct drm_device *dev);
 int ilk_wm_max_level(const struct drm_device *dev);
 void intel_update_watermarks(struct drm_crtc *crtc);
 void intel_init_pm(struct drm_device *dev);
+void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_device *dev);
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_teardown(void);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d7aef17..4f4b402 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7097,8 +7097,7 @@ void intel_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (dev_priv->display.init_clock_gating)
-		dev_priv->display.init_clock_gating(dev);
+	dev_priv->display.init_clock_gating(dev);
 }
 
 void intel_suspend_hw(struct drm_device *dev)
@@ -7107,6 +7106,61 @@ void intel_suspend_hw(struct drm_device *dev)
 		lpt_suspend_hw(dev);
 }
 
+static void nop_init_clock_gating(struct drm_device *dev)
+{
+	DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
+}
+
+/**
+ * intel_init_clock_gating_hooks - setup the clock gating hooks
+ * @dev_priv: device private
+ *
+ * Setup the hooks that configure which clocks of a given platform can be
+ * gated and also apply various GT and display specific workarounds for these
+ * platforms. Note that some GT specific workarounds are applied separately
+ * when GPU contexts or batchbuffers start their execution.
+ */
+void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
+{
+	if (IS_SKYLAKE(dev_priv))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	else if (IS_KABYLAKE(dev_priv))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	else if (IS_BROXTON(dev_priv))
+		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+	else if (IS_BROADWELL(dev_priv))
+		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
+	else if (IS_CHERRYVIEW(dev_priv))
+		dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
+	else if (IS_HASWELL(dev_priv))
+		dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+	else if (IS_IVYBRIDGE(dev_priv))
+		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+	else if (IS_VALLEYVIEW(dev_priv))
+		dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
+	else if (IS_GEN6(dev_priv))
+		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+	else if (IS_GEN5(dev_priv))
+		dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
+	else if (IS_G4X(dev_priv))
+		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+	else if (IS_CRESTLINE(dev_priv))
+		dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+	else if (IS_BROADWATER(dev_priv))
+		dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+	else if (IS_GEN3(dev_priv))
+		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
+		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+	else if (IS_GEN2(dev_priv))
+		dev_priv->display.init_clock_gating = i830_init_clock_gating;
+	else {
+		MISSING_CASE(INTEL_DEVID(dev_priv));
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	}
+
+}
+
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_device *dev)
 {
@@ -7123,10 +7177,6 @@ void intel_init_pm(struct drm_device *dev)
 	/* For FIFO watermark updates */
 	if (INTEL_INFO(dev)->gen >= 9) {
 		skl_setup_wm_latency(dev);
-
-		if (IS_BROXTON(dev))
-			dev_priv->display.init_clock_gating =
-				bxt_init_clock_gating;
 		dev_priv->display.update_wm = skl_update_wm;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		ilk_setup_wm_latency(dev);
@@ -7146,29 +7196,12 @@ void intel_init_pm(struct drm_device *dev)
 			DRM_DEBUG_KMS("Failed to read display plane latency. "
 				      "Disable CxSR\n");
 		}
-
-		if (IS_GEN5(dev))
-			dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
-		else if (IS_GEN6(dev))
-			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
-		else if (IS_IVYBRIDGE(dev))
-			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
-		else if (IS_HASWELL(dev))
-			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
-		else if (INTEL_INFO(dev)->gen == 8)
-			dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
 	} else if (IS_CHERRYVIEW(dev)) {
 		vlv_setup_wm_latency(dev);
-
 		dev_priv->display.update_wm = vlv_update_wm;
-		dev_priv->display.init_clock_gating =
-			cherryview_init_clock_gating;
 	} else if (IS_VALLEYVIEW(dev)) {
 		vlv_setup_wm_latency(dev);
-
 		dev_priv->display.update_wm = vlv_update_wm;
-		dev_priv->display.init_clock_gating =
-			valleyview_init_clock_gating;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
@@ -7184,20 +7217,13 @@ void intel_init_pm(struct drm_device *dev)
 			dev_priv->display.update_wm = NULL;
 		} else
 			dev_priv->display.update_wm = pineview_update_wm;
-		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
 	} else if (IS_G4X(dev)) {
 		dev_priv->display.update_wm = g4x_update_wm;
-		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
 	} else if (IS_GEN4(dev)) {
 		dev_priv->display.update_wm = i965_update_wm;
-		if (IS_CRESTLINE(dev))
-			dev_priv->display.init_clock_gating = crestline_init_clock_gating;
-		else if (IS_BROADWATER(dev))
-			dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
 	} else if (IS_GEN3(dev)) {
 		dev_priv->display.update_wm = i9xx_update_wm;
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
-		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
 	} else if (IS_GEN2(dev)) {
 		if (INTEL_INFO(dev)->num_pipes == 1) {
 			dev_priv->display.update_wm = i845_update_wm;
@@ -7206,11 +7232,6 @@ void intel_init_pm(struct drm_device *dev)
 			dev_priv->display.update_wm = i9xx_update_wm;
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 		}
-
-		if (IS_I85X(dev) || IS_I865G(dev))
-			dev_priv->display.init_clock_gating = i85x_init_clock_gating;
-		else
-			dev_priv->display.init_clock_gating = i830_init_clock_gating;
 	} else {
 		DRM_ERROR("unexpected fall-through in intel_init_pm\n");
 	}
-- 
2.5.0

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[PATCH v3 06/19] drm/i915: Move load time runtime device info init earlier

[Imre Deak]

This init step accesses the device, but doesn't have any device
specific side effect. It also sets up some platform specific
attributes that may be required early, so move it earlier.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 60e8fe6..da96ccd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1057,6 +1057,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_uncore_init(dev);
 
+	intel_device_info_runtime_init(dev);
+
 	ret = i915_gem_gtt_init(dev);
 	if (ret)
 		goto out_uncore_fini;
@@ -1131,8 +1133,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 			DRM_DEBUG_DRIVER("can't enable MSI");
 	}
 
-	intel_device_info_runtime_init(dev);
-
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
-- 
2.5.0

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[PATCH v3 07/19] drm/i915: Move load time gem_load_init earlier

[Imre Deak]

The only steps requiring device access is the fence and swizzling
initialization, so split these out keeping them in their current place
and move the rest of init steps earlier.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 13 ++++++++-----
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 34 ++++++++++++++++++++--------------
 3 files changed, 29 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index da96ccd..9ada500 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_init_display_hooks(dev_priv);
 	intel_init_clock_gating_hooks(dev_priv);
 	intel_init_audio_hooks(dev_priv);
+	i915_gem_load_init(dev);
 
 	intel_runtime_pm_get(dev_priv);
 
@@ -1114,7 +1115,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_opregion_setup(dev);
 
-	i915_gem_load_init(dev);
+	i915_gem_load_init_fences(dev_priv);
+	i915_gem_detect_bit_6_swizzle(dev);
+
 	i915_gem_shrinker_init(dev_priv);
 
 	/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -1136,7 +1139,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
-			goto out_gem_unload;
+			goto out_cleanup_shrinker;
 	}
 
 	ret = i915_load_modeset_init(dev);
@@ -1174,7 +1177,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 out_power_well:
 	intel_power_domains_fini(dev_priv);
 	drm_vblank_cleanup(dev);
-out_gem_unload:
+out_cleanup_shrinker:
 	i915_gem_shrinker_cleanup(dev_priv);
 
 	if (dev->pdev->msi_enabled)
@@ -1190,9 +1193,9 @@ out_uncore_fini:
 	i915_mmio_cleanup(dev);
 put_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
-	i915_gem_load_cleanup(dev);
 out_runtime_pm_put:
 	intel_runtime_pm_put(dev_priv);
+	i915_gem_load_cleanup(dev);
 	i915_workqueues_cleanup(dev_priv);
 out_free_priv:
 	kfree(dev_priv);
@@ -1277,8 +1280,8 @@ int i915_driver_unload(struct drm_device *dev)
 	intel_uncore_fini(dev);
 	i915_mmio_cleanup(dev);
 
-	i915_gem_load_cleanup(dev);
 	pci_dev_put(dev_priv->bridge_dev);
+	i915_gem_load_cleanup(dev);
 	i915_workqueues_cleanup(dev_priv);
 	kfree(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80b14f1..25274e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2836,6 +2836,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 void i915_gem_load_init(struct drm_device *dev);
 void i915_gem_load_cleanup(struct drm_device *dev);
+void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
 void *i915_gem_object_alloc(struct drm_device *dev);
 void i915_gem_object_free(struct drm_i915_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b854af2..3dab0d6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5029,6 +5029,26 @@ init_ring_lists(struct intel_engine_cs *ring)
 }
 
 void
+i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
+{
+	if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+	    !IS_CHERRYVIEW(dev_priv))
+		dev_priv->num_fence_regs = 32;
+	else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
+		 IS_I945GM(dev_priv) || IS_G33(dev_priv))
+		dev_priv->num_fence_regs = 16;
+	else
+		dev_priv->num_fence_regs = 8;
+
+	if (intel_vgpu_active(dev_priv->dev))
+		dev_priv->num_fence_regs =
+				I915_READ(vgtif_reg(avail_rs.fence_num));
+
+	/* Initialize fence registers to zero */
+	i915_gem_restore_fences(dev_priv->dev);
+}
+
+void
 i915_gem_load_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5067,17 +5087,6 @@ i915_gem_load_init(struct drm_device *dev)
 
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
-		dev_priv->num_fence_regs = 32;
-	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-		dev_priv->num_fence_regs = 16;
-	else
-		dev_priv->num_fence_regs = 8;
-
-	if (intel_vgpu_active(dev))
-		dev_priv->num_fence_regs =
-				I915_READ(vgtif_reg(avail_rs.fence_num));
-
 	/*
 	 * Set initial sequence number for requests.
 	 * Using this number allows the wraparound to happen early,
@@ -5086,11 +5095,8 @@ i915_gem_load_init(struct drm_device *dev)
 	dev_priv->next_seqno = ((u32)~0 - 0x1100);
 	dev_priv->last_seqno = ((u32)~0 - 0x1101);
 
-	/* Initialize fence registers to zero */
 	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
-	i915_gem_restore_fences(dev);
 
-	i915_gem_detect_bit_6_swizzle(dev);
 	init_waitqueue_head(&dev_priv->pending_flip_queue);
 
 	dev_priv->mm.interruptible = true;
-- 
2.5.0

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Re: [PATCH v3 07/19] drm/i915: Move load time gem_load_init earlier

[Chris Wilson]

On Wed, Mar 16, 2016 at 01:38:56PM +0200, Imre Deak wrote:
> The only steps requiring device access is the fence and swizzling
> initialization, so split these out keeping them in their current place
> and move the rest of init steps earlier.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 13 ++++++++-----
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_gem.c | 34 ++++++++++++++++++++--------------
>  3 files changed, 29 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index da96ccd..9ada500 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	intel_init_display_hooks(dev_priv);
>  	intel_init_clock_gating_hooks(dev_priv);
>  	intel_init_audio_hooks(dev_priv);
> +	i915_gem_load_init(dev);
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> @@ -1114,7 +1115,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  
>  	intel_opregion_setup(dev);
>  
> -	i915_gem_load_init(dev);
> +	i915_gem_load_init_fences(dev_priv);
> +	i915_gem_detect_bit_6_swizzle(dev);

Pedant in me would say we want to detect the hw fence capabilties first.
Just move i915_gem_detect_bit_6_swizzle() into init_fences since they
are semantically related.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH v3 07/19] drm/i915: Move load time gem_load_init earlier

[Imre Deak]

On Wed, 2016-03-16 at 11:57 +0000, Chris Wilson wrote:
> On Wed, Mar 16, 2016 at 01:38:56PM +0200, Imre Deak wrote:
> > The only steps requiring device access is the fence and swizzling
> > initialization, so split these out keeping them in their current
> > place
> > and move the rest of init steps earlier.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_dma.c | 13 ++++++++-----
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/i915_gem.c | 34 ++++++++++++++++++++---------
> > -----
> >  3 files changed, 29 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index da96ccd..9ada500 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> >  	intel_init_display_hooks(dev_priv);
> >  	intel_init_clock_gating_hooks(dev_priv);
> >  	intel_init_audio_hooks(dev_priv);
> > +	i915_gem_load_init(dev);
> >  
> >  	intel_runtime_pm_get(dev_priv);
> >  
> > @@ -1114,7 +1115,9 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> >  
> >  	intel_opregion_setup(dev);
> >  
> > -	i915_gem_load_init(dev);
> > +	i915_gem_load_init_fences(dev_priv);
> > +	i915_gem_detect_bit_6_swizzle(dev);
> 
> Pedant in me would say we want to detect the hw fence capabilties
> first.
> Just move i915_gem_detect_bit_6_swizzle() into init_fences since they
> are semantically related.

Ok.

--Imre
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[PATCH v4 07/19] drm/i915: Move load time gem_load_init earlier

[Imre Deak]

The only steps requiring device access is the fence and swizzling
initialization, so split these out keeping them in their current place
and move the rest of init steps earlier.

v2-v3:
- unchanged
v4:
- move call to i915_gem_detect_bit_6_swizzle() to
  i915_gem_load_init_fences() and preserve the original order of
  the detection of HW fence capailities wrt. swizzling (Chris)

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_dma.c | 12 +++++++-----
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 38 ++++++++++++++++++++++++--------------
 3 files changed, 32 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index da96ccd..0e68f1e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_init_display_hooks(dev_priv);
 	intel_init_clock_gating_hooks(dev_priv);
 	intel_init_audio_hooks(dev_priv);
+	i915_gem_load_init(dev);
 
 	intel_runtime_pm_get(dev_priv);
 
@@ -1114,7 +1115,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_opregion_setup(dev);
 
-	i915_gem_load_init(dev);
+	i915_gem_load_init_fences(dev_priv);
+
 	i915_gem_shrinker_init(dev_priv);
 
 	/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -1136,7 +1138,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
-			goto out_gem_unload;
+			goto out_cleanup_shrinker;
 	}
 
 	ret = i915_load_modeset_init(dev);
@@ -1174,7 +1176,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 out_power_well:
 	intel_power_domains_fini(dev_priv);
 	drm_vblank_cleanup(dev);
-out_gem_unload:
+out_cleanup_shrinker:
 	i915_gem_shrinker_cleanup(dev_priv);
 
 	if (dev->pdev->msi_enabled)
@@ -1190,9 +1192,9 @@ out_uncore_fini:
 	i915_mmio_cleanup(dev);
 put_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
-	i915_gem_load_cleanup(dev);
 out_runtime_pm_put:
 	intel_runtime_pm_put(dev_priv);
+	i915_gem_load_cleanup(dev);
 	i915_workqueues_cleanup(dev_priv);
 out_free_priv:
 	kfree(dev_priv);
@@ -1277,8 +1279,8 @@ int i915_driver_unload(struct drm_device *dev)
 	intel_uncore_fini(dev);
 	i915_mmio_cleanup(dev);
 
-	i915_gem_load_cleanup(dev);
 	pci_dev_put(dev_priv->bridge_dev);
+	i915_gem_load_cleanup(dev);
 	i915_workqueues_cleanup(dev_priv);
 	kfree(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80b14f1..25274e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2836,6 +2836,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 void i915_gem_load_init(struct drm_device *dev);
 void i915_gem_load_cleanup(struct drm_device *dev);
+void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
 void *i915_gem_object_alloc(struct drm_device *dev);
 void i915_gem_object_free(struct drm_i915_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b854af2..07848f8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5029,6 +5029,30 @@ init_ring_lists(struct intel_engine_cs *ring)
 }
 
 void
+i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+	    !IS_CHERRYVIEW(dev_priv))
+		dev_priv->num_fence_regs = 32;
+	else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
+		 IS_I945GM(dev_priv) || IS_G33(dev_priv))
+		dev_priv->num_fence_regs = 16;
+	else
+		dev_priv->num_fence_regs = 8;
+
+	if (intel_vgpu_active(dev))
+		dev_priv->num_fence_regs =
+				I915_READ(vgtif_reg(avail_rs.fence_num));
+
+	/* Initialize fence registers to zero */
+	i915_gem_restore_fences(dev);
+
+	i915_gem_detect_bit_6_swizzle(dev);
+}
+
+void
 i915_gem_load_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5067,17 +5091,6 @@ i915_gem_load_init(struct drm_device *dev)
 
 	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
-		dev_priv->num_fence_regs = 32;
-	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-		dev_priv->num_fence_regs = 16;
-	else
-		dev_priv->num_fence_regs = 8;
-
-	if (intel_vgpu_active(dev))
-		dev_priv->num_fence_regs =
-				I915_READ(vgtif_reg(avail_rs.fence_num));
-
 	/*
 	 * Set initial sequence number for requests.
 	 * Using this number allows the wraparound to happen early,
@@ -5086,11 +5099,8 @@ i915_gem_load_init(struct drm_device *dev)
 	dev_priv->next_seqno = ((u32)~0 - 0x1100);
 	dev_priv->last_seqno = ((u32)~0 - 0x1101);
 
-	/* Initialize fence registers to zero */
 	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
-	i915_gem_restore_fences(dev);
 
-	i915_gem_detect_bit_6_swizzle(dev);
 	init_waitqueue_head(&dev_priv->pending_flip_queue);
 
 	dev_priv->mm.interruptible = true;
-- 
2.5.0

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[PATCH v3 08/19] drm/i915: Move load time runtime PM get later

[Imre Deak]

We require the device to be powered only before accessing it, so we can
move this call later.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9ada500..93b9839 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1033,8 +1033,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	intel_init_audio_hooks(dev_priv);
 	i915_gem_load_init(dev);
 
-	intel_runtime_pm_get(dev_priv);
-
 	intel_display_crc_init(dev);
 
 	i915_dump_device_info(dev_priv);
@@ -1047,6 +1045,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 		DRM_INFO("This is an early pre-production Haswell machine. "
 			 "It may not be fully functional.\n");
 
+	intel_runtime_pm_get(dev_priv);
+
 	if (i915_get_bridge_dev(dev)) {
 		ret = -EIO;
 		goto out_runtime_pm_put;
-- 
2.5.0

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[PATCH v3 09/19] drm/i915: Move load time shrinker registration later

[Imre Deak]

According to the new init phases scheme we should register the driver
with frameworks/userspace only one the device is setup fully. So move
the shrinker registration later accordingly.

Also fix the shrinker unregistration order wrt. the acpi unregistration
to fix the corresponding init order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 93b9839..346ed8e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1118,8 +1118,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	i915_gem_load_init_fences(dev_priv);
 	i915_gem_detect_bit_6_swizzle(dev);
 
-	i915_gem_shrinker_init(dev_priv);
-
 	/* On the 945G/GM, the chipset reports the MSI capability on the
 	 * integrated graphics even though the support isn't actually there
 	 * according to the published specs.  It doesn't appear to function
@@ -1139,7 +1137,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
-			goto out_cleanup_shrinker;
+			goto out_disable_msi;
 	}
 
 	ret = i915_load_modeset_init(dev);
@@ -1148,6 +1146,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 		goto out_power_well;
 	}
 
+	i915_gem_shrinker_init(dev_priv);
 	/*
 	 * Notify a valid surface after modesetting,
 	 * when running inside a VM.
@@ -1177,9 +1176,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 out_power_well:
 	intel_power_domains_fini(dev_priv);
 	drm_vblank_cleanup(dev);
-out_cleanup_shrinker:
-	i915_gem_shrinker_cleanup(dev_priv);
-
+out_disable_msi:
 	if (dev->pdev->msi_enabled)
 		pci_disable_msi(dev->pdev);
 
@@ -1224,12 +1221,11 @@ int i915_driver_unload(struct drm_device *dev)
 
 	i915_teardown_sysfs(dev);
 
-	i915_gem_shrinker_cleanup(dev_priv);
-
 	io_mapping_free(dev_priv->gtt.mappable);
 	arch_phys_wc_del(dev_priv->gtt.mtrr);
 
 	acpi_video_unregister();
+	i915_gem_shrinker_cleanup(dev_priv);
 
 	drm_vblank_cleanup(dev);
 
-- 
2.5.0

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[PATCH v3 10/19] drm/i915: Move load time audio component registration earlier

[Imre Deak]

We should register all the interfaces before we enable runtime PM.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 346ed8e..da1bea8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1165,10 +1165,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (IS_GEN5(dev))
 		intel_gpu_ips_init(dev_priv);
 
-	intel_runtime_pm_enable(dev_priv);
-
 	i915_audio_component_init(dev_priv);
 
+	intel_runtime_pm_enable(dev_priv);
+
 	intel_runtime_pm_put(dev_priv);
 
 	return 0;
@@ -1207,8 +1207,6 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_fbdev_fini(dev);
 
-	i915_audio_component_cleanup(dev_priv);
-
 	ret = i915_gem_suspend(dev);
 	if (ret) {
 		DRM_ERROR("failed to idle hardware: %d\n", ret);
@@ -1217,6 +1215,8 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_power_domains_fini(dev_priv);
 
+	i915_audio_component_cleanup(dev_priv);
+
 	intel_gpu_ips_teardown();
 
 	i915_teardown_sysfs(dev);
-- 
2.5.0

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[PATCH v3 11/19] drm/i915: Move unload time display power domain uninit later

[Imre Deak]

Move the power domain uninitialization later so that it matches its
corresponding init order. Since we access the HW during the later
unitialization steps keep a wake reference until after the last such
step.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index da1bea8..b50d111 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1213,7 +1213,7 @@ int i915_driver_unload(struct drm_device *dev)
 		return ret;
 	}
 
-	intel_power_domains_fini(dev_priv);
+	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
 	i915_audio_component_cleanup(dev_priv);
 
@@ -1269,6 +1269,8 @@ int i915_driver_unload(struct drm_device *dev)
 	mutex_unlock(&dev->struct_mutex);
 	intel_fbc_cleanup_cfb(dev_priv);
 
+	intel_power_domains_fini(dev_priv);
+
 	pm_qos_remove_request(&dev_priv->pm_qos);
 
 	i915_global_gtt_cleanup(dev);
@@ -1277,6 +1279,9 @@ int i915_driver_unload(struct drm_device *dev)
 	i915_mmio_cleanup(dev);
 
 	pci_dev_put(dev_priv->bridge_dev);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+
 	i915_gem_load_cleanup(dev);
 	i915_workqueues_cleanup(dev_priv);
 	kfree(dev_priv);
-- 
2.5.0

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[PATCH v3 12/19] drm/i915: Move unload time GTT, MSI IRQ cleanup later

[Imre Deak]

Move the GTT,MSI IRQ cleanup later so that it matches their
corresponding init order. Also fix the order of these calls wrt. each
other to match their corresponding init order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index b50d111..7ab8ac5 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1221,9 +1221,6 @@ int i915_driver_unload(struct drm_device *dev)
 
 	i915_teardown_sysfs(dev);
 
-	io_mapping_free(dev_priv->gtt.mappable);
-	arch_phys_wc_del(dev_priv->gtt.mtrr);
-
 	acpi_video_unregister();
 	i915_gem_shrinker_cleanup(dev_priv);
 
@@ -1254,9 +1251,6 @@ int i915_driver_unload(struct drm_device *dev)
 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 	i915_destroy_error_state(dev);
 
-	if (dev->pdev->msi_enabled)
-		pci_disable_msi(dev->pdev);
-
 	intel_opregion_fini(dev);
 
 	/* Flush any outstanding unpin_work. */
@@ -1271,8 +1265,11 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_power_domains_fini(dev_priv);
 
+	if (dev->pdev->msi_enabled)
+		pci_disable_msi(dev->pdev);
 	pm_qos_remove_request(&dev_priv->pm_qos);
-
+	arch_phys_wc_del(dev_priv->gtt.mtrr);
+	io_mapping_free(dev_priv->gtt.mappable);
 	i915_global_gtt_cleanup(dev);
 
 	intel_uncore_fini(dev);
-- 
2.5.0

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[PATCH v3 13/19] drm/i915: Move unload time opregion unregistration earlier

[Imre Deak]

Move the opregion unregistration earlier to match its corresponding
registration order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 7ab8ac5..e2465c6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1222,6 +1222,7 @@ int i915_driver_unload(struct drm_device *dev)
 	i915_teardown_sysfs(dev);
 
 	acpi_video_unregister();
+	intel_opregion_fini(dev);
 	i915_gem_shrinker_cleanup(dev_priv);
 
 	drm_vblank_cleanup(dev);
@@ -1251,8 +1252,6 @@ int i915_driver_unload(struct drm_device *dev)
 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 	i915_destroy_error_state(dev);
 
-	intel_opregion_fini(dev);
-
 	/* Flush any outstanding unpin_work. */
 	flush_workqueue(dev_priv->wq);
 
-- 
2.5.0

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[PATCH v3 14/19] drm/i915: Split out load time early initialization

[Imre Deak]

According to the new init phases scheme we should initialize "SW-only"
state not requiring accessing the device as the very first step, so that
the reasoning about dependencies of later steps becomes easier. So move
these init steps into a separate function. This also has the benefit of
making the error path cleaner both in the new function and int
i915_driver_load()/unload().

No functional change.

Suggested by Chris.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 130 +++++++++++++++++++++++++---------------
 1 file changed, 81 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e2465c6..93e7951 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -933,6 +933,83 @@ static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 	destroy_workqueue(dev_priv->wq);
 }
 
+/**
+ * i915_driver_init_early - setup state not requiring device access
+ * @dev_priv: device private
+ *
+ * Initialize everything that is a "SW-only" state, that is state not
+ * requiring accessing the device or exposing the driver via kernel internal
+ * or userspace interfaces. Example steps belonging here: lock initialization,
+ * system memory allocation, setting up device specific attributes and
+ * function hooks not requiring accessing the device.
+ */
+static int i915_driver_init_early(struct drm_i915_private *dev_priv,
+				  struct drm_device *dev,
+				  struct intel_device_info *info)
+{
+	struct intel_device_info *device_info;
+	int ret = 0;
+
+	dev_priv->dev = dev;
+
+	/* Setup the write-once "constant" device info */
+	device_info = (struct intel_device_info *)&dev_priv->info;
+	memcpy(device_info, info, sizeof(dev_priv->info));
+	device_info->device_id = dev->pdev->device;
+
+	spin_lock_init(&dev_priv->irq_lock);
+	spin_lock_init(&dev_priv->gpu_error.lock);
+	mutex_init(&dev_priv->backlight_lock);
+	spin_lock_init(&dev_priv->uncore.lock);
+	spin_lock_init(&dev_priv->mm.object_stat_lock);
+	spin_lock_init(&dev_priv->mmio_flip_lock);
+	mutex_init(&dev_priv->sb_lock);
+	mutex_init(&dev_priv->modeset_restore_lock);
+	mutex_init(&dev_priv->av_mutex);
+	mutex_init(&dev_priv->wm.wm_mutex);
+	mutex_init(&dev_priv->pps_mutex);
+
+	ret = i915_workqueues_init(dev_priv);
+	if (ret < 0)
+		return ret;
+
+	/* This must be called before any calls to HAS_PCH_* */
+	intel_detect_pch(dev);
+
+	intel_pm_setup(dev);
+	intel_init_dpio(dev_priv);
+	intel_power_domains_init(dev_priv);
+	intel_irq_init(dev_priv);
+	intel_init_display_hooks(dev_priv);
+	intel_init_clock_gating_hooks(dev_priv);
+	intel_init_audio_hooks(dev_priv);
+	i915_gem_load_init(dev);
+
+	intel_display_crc_init(dev);
+
+	i915_dump_device_info(dev_priv);
+
+	/* Not all pre-production machines fall into this category, only the
+	 * very first ones. Almost everything should work, except for maybe
+	 * suspend/resume. And we don't implement workarounds that affect only
+	 * pre-production machines. */
+	if (IS_HSW_EARLY_SDV(dev))
+		DRM_INFO("This is an early pre-production Haswell machine. "
+			 "It may not be fully functional.\n");
+
+	return 0;
+}
+
+/**
+ * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
+ * @dev_priv: device private
+ */
+static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
+{
+	i915_gem_load_cleanup(dev_priv->dev);
+	i915_workqueues_cleanup(dev_priv);
+}
+
 static int i915_mmio_setup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -987,64 +1064,21 @@ static void i915_mmio_cleanup(struct drm_device *dev)
 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
 	struct drm_i915_private *dev_priv;
-	struct intel_device_info *info, *device_info;
 	int ret = 0;
 	uint32_t aperture_size;
 
-	info = (struct intel_device_info *) flags;
-
 	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 	if (dev_priv == NULL)
 		return -ENOMEM;
 
 	dev->dev_private = dev_priv;
-	dev_priv->dev = dev;
 
-	/* Setup the write-once "constant" device info */
-	device_info = (struct intel_device_info *)&dev_priv->info;
-	memcpy(device_info, info, sizeof(dev_priv->info));
-	device_info->device_id = dev->pdev->device;
+	ret = i915_driver_init_early(dev_priv, dev,
+				     (struct intel_device_info *)flags);
 
-	spin_lock_init(&dev_priv->irq_lock);
-	spin_lock_init(&dev_priv->gpu_error.lock);
-	mutex_init(&dev_priv->backlight_lock);
-	spin_lock_init(&dev_priv->uncore.lock);
-	spin_lock_init(&dev_priv->mm.object_stat_lock);
-	spin_lock_init(&dev_priv->mmio_flip_lock);
-	mutex_init(&dev_priv->sb_lock);
-	mutex_init(&dev_priv->modeset_restore_lock);
-	mutex_init(&dev_priv->av_mutex);
-	mutex_init(&dev_priv->wm.wm_mutex);
-	mutex_init(&dev_priv->pps_mutex);
-
-	ret = i915_workqueues_init(dev_priv);
 	if (ret < 0)
 		goto out_free_priv;
 
-	/* This must be called before any calls to HAS_PCH_* */
-	intel_detect_pch(dev);
-
-	intel_pm_setup(dev);
-	intel_init_dpio(dev_priv);
-	intel_power_domains_init(dev_priv);
-	intel_irq_init(dev_priv);
-	intel_init_display_hooks(dev_priv);
-	intel_init_clock_gating_hooks(dev_priv);
-	intel_init_audio_hooks(dev_priv);
-	i915_gem_load_init(dev);
-
-	intel_display_crc_init(dev);
-
-	i915_dump_device_info(dev_priv);
-
-	/* Not all pre-production machines fall into this category, only the
-	 * very first ones. Almost everything should work, except for maybe
-	 * suspend/resume. And we don't implement workarounds that affect only
-	 * pre-production machines. */
-	if (IS_HSW_EARLY_SDV(dev))
-		DRM_INFO("This is an early pre-production Haswell machine. "
-			 "It may not be fully functional.\n");
-
 	intel_runtime_pm_get(dev_priv);
 
 	if (i915_get_bridge_dev(dev)) {
@@ -1192,8 +1226,7 @@ put_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
 out_runtime_pm_put:
 	intel_runtime_pm_put(dev_priv);
-	i915_gem_load_cleanup(dev);
-	i915_workqueues_cleanup(dev_priv);
+	i915_driver_cleanup_early(dev_priv);
 out_free_priv:
 	kfree(dev_priv);
 
@@ -1278,8 +1311,7 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
-	i915_gem_load_cleanup(dev);
-	i915_workqueues_cleanup(dev_priv);
+	i915_driver_cleanup_early(dev_priv);
 	kfree(dev_priv);
 
 	return 0;
-- 
2.5.0

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[PATCH v3 15/19] drm/i915: Split out load time MMIO initialization

[Imre Deak]

According to the new init phases scheme we should have a definite step
in the init sequence where MMIO access is setup, so move the
corresponding code to a separate function. This also has the benefit of
making the error path cleaner both in the new function and in
i915_driver_load()/unload().

No functional change.

Suggested by Chris.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 69 +++++++++++++++++++++++++++++------------
 1 file changed, 50 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 93e7951..ab97404 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1051,6 +1051,50 @@ static void i915_mmio_cleanup(struct drm_device *dev)
 }
 
 /**
+ * i915_driver_init_mmio - setup device MMIO
+ * @dev_priv: device private
+ *
+ * Setup minimal device state necessary for MMIO accesses later in the
+ * initialization sequence. The setup here should avoid any other device-wide
+ * side effects or exposing the driver via kernel internal or user space
+ * interfaces.
+ */
+static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	int ret;
+
+	if (i915_get_bridge_dev(dev))
+		return -EIO;
+
+	ret = i915_mmio_setup(dev);
+	if (ret < 0)
+		goto put_bridge;
+
+	intel_uncore_init(dev);
+
+	return 0;
+
+put_bridge:
+	pci_dev_put(dev_priv->bridge_dev);
+
+	return ret;
+}
+
+/**
+ * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
+ * @dev_priv: device private
+ */
+static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	intel_uncore_fini(dev);
+	i915_mmio_cleanup(dev);
+	pci_dev_put(dev_priv->bridge_dev);
+}
+
+/**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
  * @flags: startup flags
@@ -1081,22 +1125,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	intel_runtime_pm_get(dev_priv);
 
-	if (i915_get_bridge_dev(dev)) {
-		ret = -EIO;
-		goto out_runtime_pm_put;
-	}
-
-	ret = i915_mmio_setup(dev);
+	ret = i915_driver_init_mmio(dev_priv);
 	if (ret < 0)
-		goto put_bridge;
-
-	intel_uncore_init(dev);
+		goto out_runtime_pm_put;
 
 	intel_device_info_runtime_init(dev);
 
 	ret = i915_gem_gtt_init(dev);
 	if (ret)
-		goto out_uncore_fini;
+		goto out_cleanup_mmio;
 
 	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
 	 * otherwise the vga fbdev driver falls over. */
@@ -1219,11 +1256,8 @@ out_disable_msi:
 	io_mapping_free(dev_priv->gtt.mappable);
 out_gtt:
 	i915_global_gtt_cleanup(dev);
-out_uncore_fini:
-	intel_uncore_fini(dev);
-	i915_mmio_cleanup(dev);
-put_bridge:
-	pci_dev_put(dev_priv->bridge_dev);
+out_cleanup_mmio:
+	i915_driver_cleanup_mmio(dev_priv);
 out_runtime_pm_put:
 	intel_runtime_pm_put(dev_priv);
 	i915_driver_cleanup_early(dev_priv);
@@ -1304,10 +1338,7 @@ int i915_driver_unload(struct drm_device *dev)
 	io_mapping_free(dev_priv->gtt.mappable);
 	i915_global_gtt_cleanup(dev);
 
-	intel_uncore_fini(dev);
-	i915_mmio_cleanup(dev);
-
-	pci_dev_put(dev_priv->bridge_dev);
+	i915_driver_cleanup_mmio(dev_priv);
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
-- 
2.5.0

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[PATCH v3 16/19] drm/i915: Split out load time HW initialization

[Imre Deak]

According to the new init phases scheme we should have a definite step
in the init sequence where we setup things requiring accessing the
device, so move the corresponding code to separate function. The steps
in this init phase should avoid exposing the driver via some interface,
which is done in the last registration init phase. This changae also
has the benefit of making the error path cleaner both in the new
function and i915_driver_load()/unload().

No functional change.

Suggested by Chris.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 122 ++++++++++++++++++++++++----------------
 1 file changed, 75 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ab97404..aaf1b17 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1095,45 +1095,23 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 }
 
 /**
- * i915_driver_load - setup chip and create an initial config
- * @dev: DRM device
- * @flags: startup flags
+ * i915_driver_init_hw - setup state requiring device access
+ * @dev_priv: device private
  *
- * The driver load routine has to do several things:
- *   - drive output discovery via intel_modeset_init()
- *   - initialize the memory manager
- *   - allocate initial config memory
- *   - setup the DRM framebuffer with the allocated memory
+ * Setup state that requires accessing the device, but doesn't require
+ * exposing the driver via kernel internal or userspace interfaces.
  */
-int i915_driver_load(struct drm_device *dev, unsigned long flags)
+static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv;
-	int ret = 0;
+	struct drm_device *dev = dev_priv->dev;
 	uint32_t aperture_size;
-
-	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
-	if (dev_priv == NULL)
-		return -ENOMEM;
-
-	dev->dev_private = dev_priv;
-
-	ret = i915_driver_init_early(dev_priv, dev,
-				     (struct intel_device_info *)flags);
-
-	if (ret < 0)
-		goto out_free_priv;
-
-	intel_runtime_pm_get(dev_priv);
-
-	ret = i915_driver_init_mmio(dev_priv);
-	if (ret < 0)
-		goto out_runtime_pm_put;
+	int ret;
 
 	intel_device_info_runtime_init(dev);
 
 	ret = i915_gem_gtt_init(dev);
 	if (ret)
-		goto out_cleanup_mmio;
+		return ret;
 
 	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
 	 * otherwise the vga fbdev driver falls over. */
@@ -1205,10 +1183,73 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 			DRM_DEBUG_DRIVER("can't enable MSI");
 	}
 
+	return 0;
+
+out_gtt:
+	i915_global_gtt_cleanup(dev);
+
+	return ret;
+}
+
+/**
+ * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
+ * @dev_priv: device private
+ */
+static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	if (dev->pdev->msi_enabled)
+		pci_disable_msi(dev->pdev);
+
+	pm_qos_remove_request(&dev_priv->pm_qos);
+	arch_phys_wc_del(dev_priv->gtt.mtrr);
+	io_mapping_free(dev_priv->gtt.mappable);
+	i915_global_gtt_cleanup(dev);
+}
+
+/**
+ * i915_driver_load - setup chip and create an initial config
+ * @dev: DRM device
+ * @flags: startup flags
+ *
+ * The driver load routine has to do several things:
+ *   - drive output discovery via intel_modeset_init()
+ *   - initialize the memory manager
+ *   - allocate initial config memory
+ *   - setup the DRM framebuffer with the allocated memory
+ */
+int i915_driver_load(struct drm_device *dev, unsigned long flags)
+{
+	struct drm_i915_private *dev_priv;
+	int ret = 0;
+
+	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
+	if (dev_priv == NULL)
+		return -ENOMEM;
+
+	dev->dev_private = dev_priv;
+
+	ret = i915_driver_init_early(dev_priv, dev,
+				     (struct intel_device_info *)flags);
+
+	if (ret < 0)
+		goto out_free_priv;
+
+	intel_runtime_pm_get(dev_priv);
+
+	ret = i915_driver_init_mmio(dev_priv);
+	if (ret < 0)
+		goto out_runtime_pm_put;
+
+	ret = i915_driver_init_hw(dev_priv);
+	if (ret < 0)
+		goto out_cleanup_mmio;
+
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
-			goto out_disable_msi;
+			goto out_cleanup_hw;
 	}
 
 	ret = i915_load_modeset_init(dev);
@@ -1247,15 +1288,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 out_power_well:
 	intel_power_domains_fini(dev_priv);
 	drm_vblank_cleanup(dev);
-out_disable_msi:
-	if (dev->pdev->msi_enabled)
-		pci_disable_msi(dev->pdev);
-
-	pm_qos_remove_request(&dev_priv->pm_qos);
-	arch_phys_wc_del(dev_priv->gtt.mtrr);
-	io_mapping_free(dev_priv->gtt.mappable);
-out_gtt:
-	i915_global_gtt_cleanup(dev);
+out_cleanup_hw:
+	i915_driver_cleanup_hw(dev_priv);
 out_cleanup_mmio:
 	i915_driver_cleanup_mmio(dev_priv);
 out_runtime_pm_put:
@@ -1331,13 +1365,7 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_power_domains_fini(dev_priv);
 
-	if (dev->pdev->msi_enabled)
-		pci_disable_msi(dev->pdev);
-	pm_qos_remove_request(&dev_priv->pm_qos);
-	arch_phys_wc_del(dev_priv->gtt.mtrr);
-	io_mapping_free(dev_priv->gtt.mappable);
-	i915_global_gtt_cleanup(dev);
-
+	i915_driver_cleanup_hw(dev_priv);
 	i915_driver_cleanup_mmio(dev_priv);
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
-- 
2.5.0

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[PATCH v3 17/19] drm/i915: Split out load time interface registration

[Imre Deak]

According to the new init phases scheme we should register the device
making it available via some kernel internal or user space interface as
the last step in the init sequence, so move the corresponding code to a
separate function.

Also add a TODO comment about code that still needs to be moved around
to one of the init phases functions depending on what the role and effect
of that code is.

No functional change, except for the reordering of the unload time
unregistration steps of sysfs wrt. acpi and opregion.

Suggested by Chris.

v3:
- rename i915_driver_init_register to i915_driver_init_frameworks
  (Chris)
- rename i915_driver_init_frameworks to i915_driver_register (Daniel)

CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 83 +++++++++++++++++++++++++++--------------
 1 file changed, 54 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index aaf1b17..a5121cd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1209,6 +1209,53 @@ static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
 }
 
 /**
+ * i915_driver_register - register the driver with the rest of the system
+ * @dev_priv: device private
+ *
+ * Perform any steps necessary to make the driver available via kernel
+ * internal or userspace interfaces.
+ */
+static void i915_driver_register(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	i915_gem_shrinker_init(dev_priv);
+	/*
+	 * Notify a valid surface after modesetting,
+	 * when running inside a VM.
+	 */
+	if (intel_vgpu_active(dev))
+		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
+
+	i915_setup_sysfs(dev);
+
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		/* Must be done after probing outputs */
+		intel_opregion_init(dev);
+		acpi_video_register();
+	}
+
+	if (IS_GEN5(dev_priv))
+		intel_gpu_ips_init(dev_priv);
+
+	i915_audio_component_init(dev_priv);
+}
+
+/**
+ * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
+ * @dev_priv: device private
+ */
+static void i915_driver_unregister(struct drm_i915_private *dev_priv)
+{
+	i915_audio_component_cleanup(dev_priv);
+	intel_gpu_ips_teardown();
+	acpi_video_unregister();
+	intel_opregion_fini(dev_priv->dev);
+	i915_teardown_sysfs(dev_priv->dev);
+	i915_gem_shrinker_cleanup(dev_priv);
+}
+
+/**
  * i915_driver_load - setup chip and create an initial config
  * @dev: DRM device
  * @flags: startup flags
@@ -1246,6 +1293,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (ret < 0)
 		goto out_cleanup_mmio;
 
+	/*
+	 * TODO: move the vblank init and parts of modeset init steps into one
+	 * of the i915_driver_init_/i915_driver_register functions according
+	 * to the role/effect of the given init step.
+	 */
 	if (INTEL_INFO(dev)->num_pipes) {
 		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 		if (ret)
@@ -1258,26 +1310,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 		goto out_power_well;
 	}
 
-	i915_gem_shrinker_init(dev_priv);
-	/*
-	 * Notify a valid surface after modesetting,
-	 * when running inside a VM.
-	 */
-	if (intel_vgpu_active(dev))
-		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
-
-	i915_setup_sysfs(dev);
-
-	if (INTEL_INFO(dev)->num_pipes) {
-		/* Must be done after probing outputs */
-		intel_opregion_init(dev);
-		acpi_video_register();
-	}
-
-	if (IS_GEN5(dev))
-		intel_gpu_ips_init(dev_priv);
-
-	i915_audio_component_init(dev_priv);
+	i915_driver_register(dev_priv);
 
 	intel_runtime_pm_enable(dev_priv);
 
@@ -1316,15 +1349,7 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
-	i915_audio_component_cleanup(dev_priv);
-
-	intel_gpu_ips_teardown();
-
-	i915_teardown_sysfs(dev);
-
-	acpi_video_unregister();
-	intel_opregion_fini(dev);
-	i915_gem_shrinker_cleanup(dev_priv);
+	i915_driver_unregister(dev_priv);
 
 	drm_vblank_cleanup(dev);
 
-- 
2.5.0

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[PATCH v3 18/19] drm/i915: Fix power domain HW state cleanup on error path

[Imre Deak]

Move the cleanup of the power domain HW state on the error path to the
same function where the corresponding init call was called from. I
noticed this problem when loading the module with load failure injection
enabled, making i915_load_modeset_init() fail.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a5121cd..c6f97a7 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -453,6 +453,7 @@ cleanup_irq:
 	intel_teardown_gmbus(dev);
 cleanup_csr:
 	intel_csr_ucode_fini(dev_priv);
+	intel_power_domains_fini(dev_priv);
 	vga_switcheroo_unregister_client(dev->pdev);
 cleanup_vga_client:
 	vga_client_register(dev->pdev, NULL, NULL, NULL);
@@ -1307,7 +1308,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	ret = i915_load_modeset_init(dev);
 	if (ret < 0) {
 		DRM_ERROR("failed to init modeset\n");
-		goto out_power_well;
+		goto out_cleanup_vblank;
 	}
 
 	i915_driver_register(dev_priv);
@@ -1318,8 +1319,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	return 0;
 
-out_power_well:
-	intel_power_domains_fini(dev_priv);
+out_cleanup_vblank:
 	drm_vblank_cleanup(dev);
 out_cleanup_hw:
 	i915_driver_cleanup_hw(dev_priv);
-- 
2.5.0

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[PATCH v3 19/19] drm/i915: Add fault injection support

[Imre Deak]

Add support for forcing an error at selected places in the driver. As an
example add 4 options to fail during driver loading.

Requested by Chris.

v2:
- Add fault point for modeset initialization
- Print debug message when injecting an error
v3:
- Rename inject_fault to inject_load_failure, rename the related macros
  and helper accordingly (Chris)
- Use a counter instead of a mask to identify the failure point (Daniel)
- Mark the module option as _unsafe and keep i915_params ordered (Joonas)

CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c    | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h    |  4 ++++
 drivers/gpu/drm/i915/i915_params.c |  5 +++++
 drivers/gpu/drm/i915/i915_params.h |  1 +
 4 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c6f97a7..caddd36 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -50,6 +50,21 @@
 #include <linux/pm_runtime.h>
 #include <linux/oom.h>
 
+static unsigned int i915_load_fail_count;
+
+bool __i915_inject_load_failure(const char *func, int line)
+{
+	if (i915_load_fail_count >= i915.inject_load_failure)
+		return false;
+
+	if (++i915_load_fail_count == i915.inject_load_failure) {
+		DRM_DEBUG_DRIVER("Injecting failure at checkpoint %u [%s:%d]\n",
+				 i915.inject_load_failure, func, line);
+		return true;
+	}
+
+	return false;
+}
 
 static int i915_getparam(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
@@ -370,6 +385,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	ret = intel_bios_init(dev_priv);
 	if (ret)
 		DRM_INFO("failed to find VBIOS tables\n");
@@ -951,6 +969,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	struct intel_device_info *device_info;
 	int ret = 0;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	dev_priv->dev = dev;
 
 	/* Setup the write-once "constant" device info */
@@ -1065,6 +1086,9 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	if (i915_get_bridge_dev(dev))
 		return -EIO;
 
@@ -1108,6 +1132,9 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	uint32_t aperture_size;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	intel_device_info_runtime_init(dev);
 
 	ret = i915_gem_gtt_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 25274e1..9cb9f36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -98,6 +98,10 @@
 #define I915_STATE_WARN_ON(x)						\
 	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 
+bool __i915_inject_load_failure(const char *func, int line);
+#define i915_inject_load_failure() \
+	__i915_inject_load_failure(__func__, __LINE__)
+
 static inline const char *yesno(bool v)
 {
 	return v ? "yes" : "no";
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 278c9c4..a0eca7f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,6 +56,7 @@ struct i915_params i915 __read_mostly = {
 	.edp_vswing = 0,
 	.enable_guc_submission = false,
 	.guc_log_level = -1,
+	.inject_load_failure = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -201,3 +202,7 @@ MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)")
 module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
 MODULE_PARM_DESC(guc_log_level,
 	"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+
+module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
+MODULE_PARM_DESC(inject_load_failure,
+	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index bd5026b..21cf179 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -49,6 +49,7 @@ struct i915_params {
 	int use_mmio_flip;
 	int mmio_debug;
 	int edp_vswing;
+	unsigned int inject_load_failure;
 	/* leave bools at the end to not create holes */
 	bool enable_hangcheck;
 	bool fastboot;
-- 
2.5.0

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Re: [PATCH v3 19/19] drm/i915: Add fault injection support

[Chris Wilson]

On Wed, Mar 16, 2016 at 01:39:08PM +0200, Imre Deak wrote:
> Add support for forcing an error at selected places in the driver. As an
> example add 4 options to fail during driver loading.
> 
> Requested by Chris.
> 
> v2:
> - Add fault point for modeset initialization
> - Print debug message when injecting an error
> v3:
> - Rename inject_fault to inject_load_failure, rename the related macros
>   and helper accordingly (Chris)
> - Use a counter instead of a mask to identify the failure point (Daniel)
> - Mark the module option as _unsafe and keep i915_params ordered (Joonas)

Now that you have something so simple to use, putting a failure point at
the start and end of each init_func is trivial (to test the local unwind
in each function as well as the global unwind).
-Chris

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Re: [PATCH v3 19/19] drm/i915: Add fault injection support

[Imre Deak]

On Wed, 2016-03-16 at 12:00 +0000, Chris Wilson wrote:
> On Wed, Mar 16, 2016 at 01:39:08PM +0200, Imre Deak wrote:
> > Add support for forcing an error at selected places in the driver.
> > As an
> > example add 4 options to fail during driver loading.
> > 
> > Requested by Chris.
> > 
> > v2:
> > - Add fault point for modeset initialization
> > - Print debug message when injecting an error
> > v3:
> > - Rename inject_fault to inject_load_failure, rename the related
> > macros
> >   and helper accordingly (Chris)
> > - Use a counter instead of a mask to identify the failure point
> > (Daniel)
> > - Mark the module option as _unsafe and keep i915_params ordered
> > (Joonas)
> 
> Now that you have something so simple to use, putting a failure point
> at
> the start and end of each init_func is trivial (to test the local
> unwind
> in each function as well as the global unwind).

Ok can do this, but again preferably as a follow-up:
i915_load_modeset_init() has pre-existing issues, the last thing I
checked was some running work item that gets scheduled after we removed
the module already (maybe the eDP VDD work). I'll track down that and
try to clean up the rest of problems I see in i915_load_modeset_init();
with those I could add the additional checkpoints you suggest.

--Imre
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Re: [PATCH v3 19/19] drm/i915: Add fault injection support

[Chris Wilson]

On Wed, Mar 16, 2016 at 02:12:35PM +0200, Imre Deak wrote:
> On Wed, 2016-03-16 at 12:00 +0000, Chris Wilson wrote:
> > On Wed, Mar 16, 2016 at 01:39:08PM +0200, Imre Deak wrote:
> > > Add support for forcing an error at selected places in the driver.
> > > As an
> > > example add 4 options to fail during driver loading.
> > > 
> > > Requested by Chris.
> > > 
> > > v2:
> > > - Add fault point for modeset initialization
> > > - Print debug message when injecting an error
> > > v3:
> > > - Rename inject_fault to inject_load_failure, rename the related
> > > macros
> > >   and helper accordingly (Chris)
> > > - Use a counter instead of a mask to identify the failure point
> > > (Daniel)
> > > - Mark the module option as _unsafe and keep i915_params ordered
> > > (Joonas)
> > 
> > Now that you have something so simple to use, putting a failure point
> > at
> > the start and end of each init_func is trivial (to test the local
> > unwind
> > in each function as well as the global unwind).
> 
> Ok can do this, but again preferably as a follow-up:
> i915_load_modeset_init() has pre-existing issues, the last thing I
> checked was some running work item that gets scheduled after we removed
> the module already (maybe the eDP VDD work). I'll track down that and
> try to clean up the rest of problems I see in i915_load_modeset_init();
> with those I could add the additional checkpoints you suggest.

Should we expose the injection fault count so that we can automate
repeating the module reload for the right number of cycles?
-Chris

-- 
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Re: [PATCH v3 19/19] drm/i915: Add fault injection support

[Imre Deak]

On Wed, 2016-03-16 at 12:44 +0000, Chris Wilson wrote:
> On Wed, Mar 16, 2016 at 02:12:35PM +0200, Imre Deak wrote:
> > On Wed, 2016-03-16 at 12:00 +0000, Chris Wilson wrote:
> > > On Wed, Mar 16, 2016 at 01:39:08PM +0200, Imre Deak wrote:
> > > > Add support for forcing an error at selected places in the
> > > > driver.
> > > > As an
> > > > example add 4 options to fail during driver loading.
> > > > 
> > > > Requested by Chris.
> > > > 
> > > > v2:
> > > > - Add fault point for modeset initialization
> > > > - Print debug message when injecting an error
> > > > v3:
> > > > - Rename inject_fault to inject_load_failure, rename the
> > > > related
> > > > macros
> > > >   and helper accordingly (Chris)
> > > > - Use a counter instead of a mask to identify the failure point
> > > > (Daniel)
> > > > - Mark the module option as _unsafe and keep i915_params
> > > > ordered
> > > > (Joonas)
> > > 
> > > Now that you have something so simple to use, putting a failure
> > > point
> > > at
> > > the start and end of each init_func is trivial (to test the local
> > > unwind
> > > in each function as well as the global unwind).
> > 
> > Ok can do this, but again preferably as a follow-up:
> > i915_load_modeset_init() has pre-existing issues, the last thing I
> > checked was some running work item that gets scheduled after we
> > removed
> > the module already (maybe the eDP VDD work). I'll track down that
> > and
> > try to clean up the rest of problems I see in
> > i915_load_modeset_init();
> > with those I could add the additional checkpoints you suggest.
> 
> Should we expose the injection fault count so that we can automate
> repeating the module reload for the right number of cycles?

Yes, can add that.

--Imre

> -Chris
> 
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[PATCH v4 19/19] drm/i915: Add fault injection support

[Imre Deak]

Add support for forcing an error at selected places in the driver. As an
example add 4 options to fail during driver loading.

Requested by Chris.

v2:
- Add fault point for modeset initialization
- Print debug message when injecting an error
v3:
- Rename inject_fault to inject_load_failure, rename the related macros
  and helper accordingly (Chris)
- Use a counter instead of a mask to identify the failure point (Daniel)
- Mark the module option as _unsafe and keep i915_params ordered (Joonas)
v4:
- Rebase on latest -nightly

CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c    | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h    |  4 ++++
 drivers/gpu/drm/i915/i915_params.c |  4 ++++
 drivers/gpu/drm/i915/i915_params.h |  1 +
 4 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index cbbcada..8b9ac44 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -50,6 +50,21 @@
 #include <linux/pm_runtime.h>
 #include <linux/oom.h>
 
+static unsigned int i915_load_fail_count;
+
+bool __i915_inject_load_failure(const char *func, int line)
+{
+	if (i915_load_fail_count >= i915.inject_load_failure)
+		return false;
+
+	if (++i915_load_fail_count == i915.inject_load_failure) {
+		DRM_DEBUG_DRIVER("Injecting failure at checkpoint %u [%s:%d]\n",
+				 i915.inject_load_failure, func, line);
+		return true;
+	}
+
+	return false;
+}
 
 static int i915_getparam(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
@@ -370,6 +385,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	ret = intel_bios_init(dev_priv);
 	if (ret)
 		DRM_INFO("failed to find VBIOS tables\n");
@@ -951,6 +969,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	struct intel_device_info *device_info;
 	int ret = 0;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	dev_priv->dev = dev;
 
 	/* Setup the write-once "constant" device info */
@@ -1065,6 +1086,9 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	if (i915_get_bridge_dev(dev))
 		return -EIO;
 
@@ -1108,6 +1132,9 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	uint32_t aperture_size;
 	int ret;
 
+	if (i915_inject_load_failure())
+		return -ENODEV;
+
 	intel_device_info_runtime_init(dev);
 
 	ret = i915_gem_gtt_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 180cae0..a518525 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -98,6 +98,10 @@
 #define I915_STATE_WARN_ON(x)						\
 	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 
+bool __i915_inject_load_failure(const char *func, int line);
+#define i915_inject_load_failure() \
+	__i915_inject_load_failure(__func__, __LINE__)
+
 static inline const char *yesno(bool v)
 {
 	return v ? "yes" : "no";
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 97691f1..1779f02 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -57,6 +57,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_guc_submission = false,
 	.guc_log_level = -1,
 	.enable_dp_mst = true,
+	.inject_load_failure = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -206,3 +207,6 @@ MODULE_PARM_DESC(guc_log_level,
 module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600);
 MODULE_PARM_DESC(enable_dp_mst,
 	"Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)");
+module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
+MODULE_PARM_DESC(inject_load_failure,
+	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 87153b0..02bc278 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -49,6 +49,7 @@ struct i915_params {
 	int use_mmio_flip;
 	int mmio_debug;
 	int edp_vswing;
+	unsigned int inject_load_failure;
 	/* leave bools at the end to not create holes */
 	bool enable_hangcheck;
 	bool fastboot;
-- 
2.5.0

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Re: [PATCH v3 00/19] Split driver init step to phases

[Chris Wilson]

On Wed, Mar 16, 2016 at 01:38:49PM +0200, Imre Deak wrote:
> This is v3 of [1]. It includes now the fault injection patches Chris
> requested and addresses comments from Daniel and Joonas. Since IGT has
> by now an updated drv_module_reload_basic too using load failure
> injection, CI hopefully catches any problems introduced by this
> patchset.
> 
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> CC: Jani Nikula <jani.nikula@intel.com>
> CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> CC: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> [1]
> https://lists.freedesktop.org/archives/intel-gfx/2016-March/089596.html
> 
> Imre Deak (19):
>   Fix MCHBAR cleanup on the driver init error path
>   drm/i915: Move load time PCH detect, DPIO, power domain SW init
>     earlier
>   drm/i915: Move load time IRQ SW init earlier
>   drm/i915: Move load time init of display/audio hooks earlier
>   drm/i915: Move load time init of clock gating hooks earlier
>   drm/i915: Move load time runtime device info init earlier
>   drm/i915: Move load time gem_load_init earlier
>   drm/i915: Move load time runtime PM get later
>   drm/i915: Move load time shrinker registration later
>   drm/i915: Move load time audio component registration earlier
>   drm/i915: Move unload time display power domain uninit later
>   drm/i915: Move unload time GTT, MSI IRQ cleanup later
>   drm/i915: Move unload time opregion unregistration earlier
>   drm/i915: Split out load time early initialization
>   drm/i915: Split out load time MMIO initialization
>   drm/i915: Split out load time HW initialization
>   drm/i915: Split out load time interface registration
>   drm/i915: Fix power domain HW state cleanup on error path
>   drm/i915: Add fault injection support

A couple of very minor tweaks, nevertheless
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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✗ Fi.CI.BAT: failure for Split driver init step to phases (rev2)

[Patchwork]

== Series Details ==

Series: Split driver init step to phases (rev2)
URL   : https://patchwork.freedesktop.org/series/4509/
State : failure

== Summary ==

Series 4509v2 Split driver init step to phases
2016-03-16T12:32:02.196998 http://patchwork.freedesktop.org/api/1.0/series/4509/revisions/2/mbox/
Applying: Fix MCHBAR cleanup on the driver init error path
Applying: drm/i915: Move load time PCH detect, DPIO, power domain SW init earlier
Applying: drm/i915: Move load time IRQ SW init earlier
Applying: drm/i915: Move load time init of display/audio hooks earlier
Applying: drm/i915: Move load time init of clock gating hooks earlier
Applying: drm/i915: Move load time runtime device info init earlier
Applying: drm/i915: Move load time gem_load_init earlier
Applying: drm/i915: Move load time runtime PM get later
Applying: drm/i915: Move load time shrinker registration later
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_dma.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_dma.c
Applying: drm/i915: Move load time audio component registration earlier
Applying: drm/i915: Move unload time display power domain uninit later
Applying: drm/i915: Move unload time GTT, MSI IRQ cleanup later
Applying: drm/i915: Move unload time opregion unregistration earlier
Applying: drm/i915: Split out load time early initialization
Applying: drm/i915: Split out load time MMIO initialization
Applying: drm/i915: Split out load time HW initialization
Applying: drm/i915: Split out load time interface registration
Applying: drm/i915: Fix power domain HW state cleanup on error path
Applying: drm/i915: Add fault injection support
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0019 drm/i915: Add fault injection support

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✗ Fi.CI.BAT: warning for Split driver init step to phases (rev3)

[Patchwork]

== Series Details ==

Series: Split driver init step to phases (rev3)
URL   : https://patchwork.freedesktop.org/series/4509/
State : warning

== Summary ==

Series 4509v3 Split driver init step to phases
http://patchwork.freedesktop.org/api/1.0/series/4509/revisions/3/mbox/

Test drv_module_reload_basic:
                pass       -> DMESG-WARN (bsw-nuc-2)
                pass       -> DMESG-WARN (skl-i5k-2)
                pass       -> DMESG-WARN (bdw-ultra)
                pass       -> DMESG-WARN (skl-i7k-2)
                pass       -> DMESG-WARN (snb-x220t)
                pass       -> DMESG-WARN (skl-nuci5)
                pass       -> DMESG-WARN (bdw-nuci7)
Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (bdw-ultra)
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (snb-x220t)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-WARN (bdw-ultra)
        Subgroup read-crc-pipe-b-frame-sequence:
                dmesg-warn -> PASS       (snb-x220t)
        Subgroup read-crc-pipe-c-frame-sequence:
                dmesg-warn -> PASS       (hsw-gt2)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                fail       -> DMESG-FAIL (snb-x220t)

bdw-nuci7        total:194  pass:181  dwarn:1   dfail:0   fail:0   skip:12 
bdw-ultra        total:194  pass:171  dwarn:2   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:194  pass:155  dwarn:2   dfail:0   fail:0   skip:37 
byt-nuc          total:194  pass:155  dwarn:4   dfail:0   fail:0   skip:35 
hsw-gt2          total:194  pass:176  dwarn:1   dfail:0   fail:0   skip:17 
skl-i5k-2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
skl-i7k-2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
skl-nuci5        total:194  pass:182  dwarn:1   dfail:0   fail:0   skip:11 
snb-x220t        total:194  pass:159  dwarn:1   dfail:1   fail:0   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1625/

8a9a911d489fe160df173580277983dac5952ed0 drm-intel-nightly: 2016y-03m-17d-10h-02m-10s UTC integration manifest
b99e15d212c0d3595ccb0ce6cc20f627f237e69d drm/i915: Add fault injection support
708025ddfa837b37845b20d05af3c73bc0c7708e drm/i915: Fix power domain HW state cleanup on error path
54ae37dff154475dfe58998bfbedad9ec837321c drm/i915: Split out load time interface registration
ad31b795a1f0d8901700ecbd63f943463d09fafa drm/i915: Split out load time HW initialization
feac61f9eb8031a61ae9734e83e9fc9b0949c6b0 drm/i915: Split out load time MMIO initialization
69df569ebb5e3f93654526f1a03efb9703d82f94 drm/i915: Split out load time early initialization
a21acc33f9510155bcc1a5001d2e2c11943b715a drm/i915: Move unload time opregion unregistration earlier
0a5a224a5da3cfd1c0e7d3e927ceefdb894083ca drm/i915: Move unload time GTT, MSI IRQ cleanup later
50da5444e07e95c40ceae1eb6521ba19214fb2c0 drm/i915: Move unload time display power domain uninit later
ac894e86af964f1902a13cbf8e4ac6c82b8e383d drm/i915: Move load time audio component registration earlier
238ec5f2a1fa9180fbcbb1e19d44d9a69e84fd3e drm/i915: Move load time shrinker registration later
6fc3970b4da1f5131ad2a04345537e101a92cd16 drm/i915: Move load time runtime PM get later
f1c9058738a0b840385e9bbe80011a97238dfd5d drm/i915: Move load time gem_load_init earlier
6d19d18371db8aa0ecd3a6165c82be9c3d785a0f drm/i915: Move load time runtime device info init earlier
58c8dfd1314f0933a1fd7e710060617d3896a198 drm/i915: Move load time init of clock gating hooks earlier
13d5acf73a511929c6a5a17974e82b7e87cdd191 drm/i915: Move load time init of display/audio hooks earlier
620da462f78e10859a5e377ff974fee178099458 drm/i915: Move load time IRQ SW init earlier
da4d68b2404298afb9b4d44c3aed415b76fc3488 drm/i915: Move load time PCH detect, DPIO, power domain SW init earlier
145e6345dbd7b52172a7280f5c92d31019f4b8ef Fix MCHBAR cleanup on the driver init error path

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Re: ✗ Fi.CI.BAT: warning for Split driver init step to phases (rev3)

[Imre Deak]

On Thu, 2016-03-17 at 11:32 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Split driver init step to phases (rev3)
> URL   : https://patchwork.freedesktop.org/series/4509/
> State : warning
> 
> == Summary ==
> 
> Series 4509v3 Split driver init step to phases
> http://patchwork.freedesktop.org/api/1.0/series/4509/revisions/3/mbox
> /
> 
> Test drv_module_reload_basic:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>                 pass       -> DMESG-WARN (skl-i5k-2)
>                 pass       -> DMESG-WARN (bdw-ultra)
>                 pass       -> DMESG-WARN (skl-i7k-2)
>                 pass       -> DMESG-WARN (snb-x220t)
>                 pass       -> DMESG-WARN (skl-nuci5)
>                 pass       -> DMESG-WARN (bdw-nuci7)

All the above are expected "*ERROR* failed to init modeset" messages
due to forcing init failures. I asked Tomi to filter these out if the
corresponding failure injection message precedes this error message.

I can't see in the above list byt-nuc and hsw-gt2 where the CI report
also show errors/WARNs: on byt-nuc it's the pre-existing
SND_HDA/pin2port WARN, on hsw-gt2 it's the above expected modeset init
error.

> Test kms_flip:
>         Subgroup basic-flip-vs-dpms:
>                 dmesg-warn -> PASS       (bdw-ultra)
>         Subgroup basic-flip-vs-wf_vblank:
>                 fail       -> PASS       (snb-x220t)
> Test kms_pipe_crc_basic:
>         Subgroup read-crc-pipe-b:
>                 pass       -> DMESG-WARN (bdw-ultra)

The watermark programming while not powered pre-existing issue.

>         Subgroup read-crc-pipe-b-frame-sequence:
>                 dmesg-warn -> PASS       (snb-x220t)
>         Subgroup read-crc-pipe-c-frame-sequence:
>                 dmesg-warn -> PASS       (hsw-gt2)
> Test pm_rpm:
>         Subgroup basic-pci-d3-state:
>                 fail       -> DMESG-FAIL (snb-x220t)

The above watermark issue.

Also not on the above list:

- A couple of tests on byt-nuc with the above SND/pin2port WARN.
- igt@gem_ringfill@basic-default-s3 on bsw-nuc-2: a complicated looking
lockdep issue during suspend among cpu_hotplug.lock (via
gen8_ggtt_insert_entries__BKL->stop_machine), struct_mutex (via
drm_gem_mmap), mmap_sem (via kernfs_fop_write), s_active (via
device_del->kernfs_remove_by_name):
https://bugs.freedesktop.org/show_bug.cgi?id=94350

> 
> bdw-
> nuci7        total:194  pass:181  dwarn:1   dfail:0   fail:0   skip:1
> 2 
> bdw-
> ultra        total:194  pass:171  dwarn:2   dfail:0   fail:0   skip:2
> 1 
> bsw-nuc-
> 2        total:194  pass:155  dwarn:2   dfail:0   fail:0   skip:37 
> byt-
> nuc          total:194  pass:155  dwarn:4   dfail:0   fail:0   skip:3
> 5 
> hsw-
> gt2          total:194  pass:176  dwarn:1   dfail:0   fail:0   skip:1
> 7 
> skl-i5k-
> 2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
> skl-i7k-
> 2        total:194  pass:170  dwarn:1   dfail:0   fail:0   skip:23 
> skl-
> nuci5        total:194  pass:182  dwarn:1   dfail:0   fail:0   skip:1
> 1 
> snb-
> x220t        total:194  pass:159  dwarn:1   dfail:1   fail:0   skip:3
> 3 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1625/
> 
> 8a9a911d489fe160df173580277983dac5952ed0 drm-intel-nightly: 2016y-
> 03m-17d-10h-02m-10s UTC integration manifest
> b99e15d212c0d3595ccb0ce6cc20f627f237e69d drm/i915: Add fault
> injection support
> 708025ddfa837b37845b20d05af3c73bc0c7708e drm/i915: Fix power domain
> HW state cleanup on error path
> 54ae37dff154475dfe58998bfbedad9ec837321c drm/i915: Split out load
> time interface registration
> ad31b795a1f0d8901700ecbd63f943463d09fafa drm/i915: Split out load
> time HW initialization
> feac61f9eb8031a61ae9734e83e9fc9b0949c6b0 drm/i915: Split out load
> time MMIO initialization
> 69df569ebb5e3f93654526f1a03efb9703d82f94 drm/i915: Split out load
> time early initialization
> a21acc33f9510155bcc1a5001d2e2c11943b715a drm/i915: Move unload time
> opregion unregistration earlier
> 0a5a224a5da3cfd1c0e7d3e927ceefdb894083ca drm/i915: Move unload time
> GTT, MSI IRQ cleanup later
> 50da5444e07e95c40ceae1eb6521ba19214fb2c0 drm/i915: Move unload time
> display power domain uninit later
> ac894e86af964f1902a13cbf8e4ac6c82b8e383d drm/i915: Move load time
> audio component registration earlier
> 238ec5f2a1fa9180fbcbb1e19d44d9a69e84fd3e drm/i915: Move load time
> shrinker registration later
> 6fc3970b4da1f5131ad2a04345537e101a92cd16 drm/i915: Move load time
> runtime PM get later
> f1c9058738a0b840385e9bbe80011a97238dfd5d drm/i915: Move load time
> gem_load_init earlier
> 6d19d18371db8aa0ecd3a6165c82be9c3d785a0f drm/i915: Move load time
> runtime device info init earlier
> 58c8dfd1314f0933a1fd7e710060617d3896a198 drm/i915: Move load time
> init of clock gating hooks earlier
> 13d5acf73a511929c6a5a17974e82b7e87cdd191 drm/i915: Move load time
> init of display/audio hooks earlier
> 620da462f78e10859a5e377ff974fee178099458 drm/i915: Move load time IRQ
> SW init earlier
> da4d68b2404298afb9b4d44c3aed415b76fc3488 drm/i915: Move load time PCH
> detect, DPIO, power domain SW init earlier
> 145e6345dbd7b52172a7280f5c92d31019f4b8ef Fix MCHBAR cleanup on the
> driver init error path
> 
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Re: ✗ Fi.CI.BAT: warning for Split driver init step to phases (rev3)

[Imre Deak]

On Thu, 2016-03-17 at 14:23 +0200, Imre Deak wrote:
> On Thu, 2016-03-17 at 11:32 +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: Split driver init step to phases (rev3)
> > URL   : https://patchwork.freedesktop.org/series/4509/
> > State : warning
> > 
> > == Summary ==
> > 
> > Series 4509v3 Split driver init step to phases
> > http://patchwork.freedesktop.org/api/1.0/series/4509/revisions/3/mb
> > ox
> > /
> > 
> > Test drv_module_reload_basic:
> >                 pass       -> DMESG-WARN (bsw-nuc-2)
> >                 pass       -> DMESG-WARN (skl-i5k-2)
> >                 pass       -> DMESG-WARN (bdw-ultra)
> >                 pass       -> DMESG-WARN (skl-i7k-2)
> >                 pass       -> DMESG-WARN (snb-x220t)
> >                 pass       -> DMESG-WARN (skl-nuci5)
> >                 pass       -> DMESG-WARN (bdw-nuci7)
> 
> All the above are expected "*ERROR* failed to init modeset" messages
> due to forcing init failures. I asked Tomi to filter these out if the
> corresponding failure injection message precedes this error message.

After discussing with Tomi and Chris the best way is to squelch the
error message from the kernel in the above case, I'll follow up with a
patch for this.

Thanks for all the feedback and review, I pushed the patchset to -dinq.

--Imre
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