From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/7] drm/i915: Include engine->last_submitted_seqno in GPU error state
Date: Wed, 06 Apr 2016 11:57:07 +0300 [thread overview]
Message-ID: <1459933027.7193.1.camel@linux.intel.com> (raw)
In-Reply-To: <1459900669-31740-1-git-send-email-chris@chris-wilson.co.uk>
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> It's useful to look at the last seqno submitted on a particular engine
> and compare it against the HWS value to check for irregularities.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++--
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a2e3af02c292..906e5424e488 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1363,8 +1363,10 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
>
> for_each_engine_id(engine, dev_priv, id) {
> seq_printf(m, "%s:\n", engine->name);
> - seq_printf(m, "\tseqno = %x [current %x]\n",
> - engine->hangcheck.seqno, seqno[id]);
> + seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
> + engine->hangcheck.seqno,
> + seqno[id],
> + engine->last_submitted_seqno);
> seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
> (long long)engine->hangcheck.acthd,
> (long long)acthd[id]);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 313bc3576d87..fad8e0d5a216 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -495,6 +495,7 @@ struct drm_i915_error_state {
> u32 cpu_ring_head;
> u32 cpu_ring_tail;
>
> + u32 last_seqno;
> u32 semaphore_seqno[I915_NUM_ENGINES - 1];
>
> /* Register state */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 9b55409d91b3..9463cb4e9323 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -296,6 +296,7 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
> }
> }
> err_printf(m, " seqno: 0x%08x\n", ring->seqno);
> + err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno);
> err_printf(m, " waiting: %s\n", yesno(ring->waiting));
> err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
> err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
> @@ -931,6 +932,7 @@ static void i915_record_ring_state(struct drm_device *dev,
> ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
> ering->seqno = engine->get_seqno(engine, false);
> ering->acthd = intel_ring_get_active_head(engine);
> + ering->last_seqno = engine->last_submitted_seqno;
> ering->start = I915_READ_START(engine);
> ering->head = I915_READ_HEAD(engine);
> ering->tail = I915_READ_TAIL(engine);
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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next prev parent reply other threads:[~2016-04-06 8:56 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-05 23:57 [PATCH 1/7] drm/i915: Include engine->last_submitted_seqno in GPU error state Chris Wilson
2016-04-05 23:57 ` [PATCH 2/7] drm/i915: On GPU reset, set the HWS breadcrumb to the last seqno Chris Wilson
2016-04-06 9:29 ` Mika Kuoppala
2016-04-06 10:40 ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 3/7] drm/i915: Remove unneeded drm_device pointer from intel_ring_init_seqno() Chris Wilson
2016-04-06 9:08 ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 4/7] drm/i915: Move the hw semaphore initialisation from GEM to the engine Chris Wilson
2016-04-06 9:29 ` Mika Kuoppala
2016-04-06 10:27 ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 5/7] drm/i915: Reset semaphore page for gen8 Chris Wilson
2016-04-06 9:58 ` Joonas Lahtinen
2016-04-06 10:10 ` Chris Wilson
2016-04-06 10:43 ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 6/7] drm/i915: Reset engine->last_submitted_seqno Chris Wilson
2016-04-06 9:30 ` Mika Kuoppala
2016-04-06 10:36 ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 7/7] drm/i915: Simplify check for idleness in hangcheck Chris Wilson
2016-04-06 9:05 ` Joonas Lahtinen
2016-04-06 9:32 ` Mika Kuoppala
2016-04-06 9:44 ` Chris Wilson
2016-04-06 8:57 ` Joonas Lahtinen [this message]
2016-04-06 8:59 ` ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Include engine->last_submitted_seqno in GPU error state Patchwork
2016-04-06 9:28 ` [PATCH 1/7] " Mika Kuoppala
2016-04-06 12:33 ` [PATCH v2 1/9] " Chris Wilson
2016-04-06 12:33 ` [PATCH v2 2/9] drm/i915: On GPU reset, set the HWS breadcrumb to the last seqno Chris Wilson
2016-04-06 12:33 ` [PATCH v2 3/9] drm/i915: Remove unneeded drm_device pointer from intel_ring_init_seqno() Chris Wilson
2016-04-06 12:33 ` [PATCH v2 4/9] drm/i915: Move the hw semaphore initialisation from GEM to the engine Chris Wilson
2016-04-07 6:24 ` Joonas Lahtinen
2016-04-06 12:33 ` [PATCH v2 5/9] drm/i915: Refactor gen8 semaphore offset calculation Chris Wilson
2016-04-07 6:23 ` Joonas Lahtinen
2016-04-06 12:33 ` [PATCH v2 6/9] drm/i915: Reset semaphore page for gen8 Chris Wilson
2016-04-07 6:21 ` Joonas Lahtinen
2016-04-06 12:33 ` [PATCH v2 7/9] drm/i915: Reset engine->last_submitted_seqno Chris Wilson
2016-04-06 12:33 ` [PATCH v2 8/9] drm/i915: Apply a mb between emitting the request and hangcheck Chris Wilson
2016-04-06 14:24 ` Mika Kuoppala
2016-04-06 12:33 ` [PATCH v2 9/9] drm/i915: Simplify check for idleness in hangcheck Chris Wilson
2016-04-06 14:24 ` Mika Kuoppala
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