From: Imre Deak <imre.deak@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/10] drm/i915: Fix up vlv/chv display irq setup
Date: Tue, 12 Apr 2016 13:12:12 +0300 [thread overview]
Message-ID: <1460455932.12168.51.camel@intel.com> (raw)
In-Reply-To: <20160412090532.GM4329@intel.com>
On ti, 2016-04-12 at 12:05 +0300, Ville Syrjälä wrote:
> On Mon, Apr 11, 2016 at 07:29:13PM +0300, Imre Deak wrote:
> > On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The vlv/chv display irq setup was a bit of mess after I ran out
> > > of steam
> > > when working on it last. Fix it up so that we just have a
> > > _reset() and
> > > _postinstall() hooks for the display irqs, and use those
> > > consistently.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++--------------
> > > ----------------
> > > 1 file changed, 24 insertions(+), 78 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 1d21ebfffd4d..a1239fedc086 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3306,13 +3306,15 @@ static void vlv_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > {
> > > enum pipe pipe;
> > >
> > > - i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
> > > + i915_hotplug_interrupt_update_locked(dev_priv,
> > > 0xffffffff, 0);
> > > I915_WRITE(PORT_HOTPLUG_STAT,
> > > I915_READ(PORT_HOTPLUG_STAT));
> > >
> > > for_each_pipe(dev_priv, pipe)
> > > I915_WRITE(PIPESTAT(pipe), 0xffff);
> >
> > Since vlv_display_irq_reset() will be used in place
> > of valleyview_display_irqs_uninstall()/i915_disable_pipestat()
> > we'll leave now stale bits in pipestat_irq_mask[pipe]. It's not a
> > problem since display_irqs_enabled effectively masks these bits,
> > but
> > for consistency I'd clear them.
>
> OTOH we can't mask PIPESTAT bits, so even if we clear them here, it's
> very likely some of the bits will be set again by the time we
> actually
> enable an interrupt.
>
> In any case, I think I'll be posting a patch to clean up the PIPESTAT
> clearing/disabling acrosss the board. It's a bit of a mess right now,
> with each platform doing things slightly differently.
Ok, you could add something about the above to the commit message. My
R-b applies in any case.
> > The same goes for clearing PIPE_FIFO_UNDERRUN_STATUS.
> >
> > With that:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > >
> > > GEN5_IRQ_RESET(VLV_);
> > > +
> > > + dev_priv->irq_mask = ~0;
> > > }
> >
> >
> >
> > >
> > > static void valleyview_irq_preinstall(struct drm_device *dev)
> > > @@ -3323,7 +3325,9 @@ static void
> > > valleyview_irq_preinstall(struct drm_device *dev)
> > >
> > > I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> > >
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > vlv_display_irq_reset(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3398,7 +3402,9 @@ static void
> > > cherryview_irq_preinstall(struct drm_device *dev)
> > >
> > > I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> > >
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > vlv_display_irq_reset(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
> > > @@ -3645,7 +3651,7 @@ static int ironlake_irq_postinstall(struct
> > > drm_device *dev)
> > > return 0;
> > > }
> > >
> > > -static void valleyview_display_irqs_install(struct
> > > drm_i915_private *dev_priv)
> > > +static void vlv_display_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > u32 pipestat_mask;
> > > u32 iir_mask;
> > > @@ -3679,40 +3685,6 @@ static void
> > > valleyview_display_irqs_install(struct drm_i915_private
> > > *dev_priv)
> > > POSTING_READ(VLV_IMR);
> > > }
> > >
> > > -static void valleyview_display_irqs_uninstall(struct
> > > drm_i915_private *dev_priv)
> > > -{
> > > - u32 pipestat_mask;
> > > - u32 iir_mask;
> > > - enum pipe pipe;
> > > -
> > > - iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> > > - I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> > > - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> > > - if (IS_CHERRYVIEW(dev_priv))
> > > - iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> > > -
> > > - dev_priv->irq_mask |= iir_mask;
> > > - I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > > - I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > > - I915_WRITE(VLV_IIR, iir_mask);
> > > - I915_WRITE(VLV_IIR, iir_mask);
> > > - POSTING_READ(VLV_IIR);
> > > -
> > > - pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> > > - PIPE_CRC_DONE_INTERRUPT_STATUS;
> > > -
> > > - i915_disable_pipestat(dev_priv, PIPE_A,
> > > PIPE_GMBUS_INTERRUPT_STATUS);
> > > - for_each_pipe(dev_priv, pipe)
> > > - i915_disable_pipestat(dev_priv, pipe,
> > > pipestat_mask);
> > > -
> > > - pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> > > - PIPE_FIFO_UNDERRUN_STATUS;
> > > -
> > > - for_each_pipe(dev_priv, pipe)
> > > - I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> > > - POSTING_READ(PIPESTAT(PIPE_A));
> > > -}
> > > -
> > > void valleyview_enable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > assert_spin_locked(&dev_priv->irq_lock);
> > > @@ -3723,7 +3695,7 @@ void valleyview_enable_display_irqs(struct
> > > drm_i915_private *dev_priv)
> > > dev_priv->display_irqs_enabled = true;
> > >
> > > if (intel_irqs_enabled(dev_priv))
> > > - valleyview_display_irqs_install(dev_priv);
> > > + vlv_display_irq_postinstall(dev_priv);
> > > }
> > >
> > > void valleyview_disable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > > @@ -3736,36 +3708,14 @@ void
> > > valleyview_disable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > > dev_priv->display_irqs_enabled = false;
> > >
> > > if (intel_irqs_enabled(dev_priv))
> > > - valleyview_display_irqs_uninstall(dev_priv);
> > > + vlv_display_irq_reset(dev_priv);
> > > }
> > >
> > > -static void vlv_display_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > -{
> > > - dev_priv->irq_mask = ~0;
> > > -
> > > - i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> > > - POSTING_READ(PORT_HOTPLUG_EN);
> > > -
> > > - I915_WRITE(VLV_IIR, 0xffffffff);
> > > - I915_WRITE(VLV_IIR, 0xffffffff);
> > > - I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > > - I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > > - POSTING_READ(VLV_IMR);
> > > -
> > > - /* Interrupt setup is already guaranteed to be single-
> > > threaded, this is
> > > - * just to make the assert_spin_locked check happy. */
> > > - spin_lock_irq(&dev_priv->irq_lock);
> > > - if (dev_priv->display_irqs_enabled)
> > > - valleyview_display_irqs_install(dev_priv);
> > > - spin_unlock_irq(&dev_priv->irq_lock);
> > > -}
> > >
> > > static int valleyview_irq_postinstall(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > >
> > > - vlv_display_irq_postinstall(dev_priv);
> > > -
> > > gen5_gt_irq_postinstall(dev);
> > >
> > > /* ack & enable invalid PTE error interrupts */
> > > @@ -3774,6 +3724,10 @@ static int
> > > valleyview_irq_postinstall(struct drm_device *dev)
> > > I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
> > > #endif
> > >
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > + vlv_display_irq_postinstall(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > +
> > > I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> > >
> > > return 0;
> > > @@ -3874,10 +3828,12 @@ static int
> > > cherryview_irq_postinstall(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > >
> > > - vlv_display_irq_postinstall(dev_priv);
> > > -
> > > gen8_gt_irq_postinstall(dev_priv);
> > >
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > + vlv_display_irq_postinstall(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > +
> > > I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> > > POSTING_READ(GEN8_MASTER_IRQ);
> > >
> > > @@ -3894,20 +3850,6 @@ static void gen8_irq_uninstall(struct
> > > drm_device *dev)
> > > gen8_irq_reset(dev);
> > > }
> > >
> > > -static void vlv_display_irq_uninstall(struct drm_i915_private
> > > *dev_priv)
> > > -{
> > > - /* Interrupt setup is already guaranteed to be single-
> > > threaded, this is
> > > - * just to make the assert_spin_locked check happy. */
> > > - spin_lock_irq(&dev_priv->irq_lock);
> > > - if (dev_priv->display_irqs_enabled)
> > > - valleyview_display_irqs_uninstall(dev_priv);
> > > - spin_unlock_irq(&dev_priv->irq_lock);
> > > -
> > > - vlv_display_irq_reset(dev_priv);
> > > -
> > > - dev_priv->irq_mask = ~0;
> > > -}
> > > -
> > > static void valleyview_irq_uninstall(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -3921,7 +3863,9 @@ static void valleyview_irq_uninstall(struct
> > > drm_device *dev)
> > >
> > > I915_WRITE(HWSTAM, 0xffffffff);
> > >
> > > - vlv_display_irq_uninstall(dev_priv);
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > + vlv_display_irq_reset(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > static void cherryview_irq_uninstall(struct drm_device *dev)
> > > @@ -3938,7 +3882,9 @@ static void cherryview_irq_uninstall(struct
> > > drm_device *dev)
> > >
> > > GEN5_IRQ_RESET(GEN8_PCU_);
> > >
> > > - vlv_display_irq_uninstall(dev_priv);
> > > + spin_lock_irq(&dev_priv->irq_lock);
> > > + vlv_display_irq_reset(dev_priv);
> > > + spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > static void ironlake_irq_uninstall(struct drm_device *dev)
>
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next prev parent reply other threads:[~2016-04-12 10:12 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-11 13:56 [PATCH 00/10] drm/i915: Fix VLV/CHV unclaimed register errors ville.syrjala
2016-04-11 13:56 ` [PATCH 01/10] drm/i915: Remove "VLV magic" from irq setup ville.syrjala
2016-04-11 15:20 ` Imre Deak
2016-04-11 15:45 ` Ville Syrjälä
2016-04-11 13:56 ` [PATCH 02/10] drm/i915: Fix up vlv/chv display " ville.syrjala
2016-04-11 16:29 ` Imre Deak
2016-04-12 9:05 ` Ville Syrjälä
2016-04-12 10:12 ` Imre Deak [this message]
2016-04-12 15:56 ` [PATCH v2 " ville.syrjala
2016-04-11 13:56 ` [PATCH 03/10] drm/i915: Skip display irq setup if display irqs aren't flagged as enabled ville.syrjala
2016-04-11 16:31 ` Imre Deak
2016-04-11 13:56 ` [PATCH 04/10] drm/i915: Move vlv/chv display irq code to a more logical place ville.syrjala
2016-04-11 16:34 ` Imre Deak
2016-04-12 15:56 ` [PATCH v2 " ville.syrjala
2016-04-11 13:56 ` [PATCH 05/10] drm/i915: Clear display interrupt before enabling when turning on the power well ville.syrjala
2016-04-11 16:36 ` Imre Deak
2016-04-11 13:56 ` [PATCH 06/10] drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall() ville.syrjala
2016-04-11 16:38 ` Imre Deak
2016-04-11 13:56 ` [PATCH 07/10] drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall ville.syrjala
2016-04-11 16:39 ` Imre Deak
2016-04-11 13:56 ` [PATCH 08/10] drm/i915: Move vlv_init_display_clock_gating() to the display power well ville.syrjala
2016-04-12 10:25 ` Imre Deak
2016-04-12 11:51 ` Ville Syrjälä
2016-04-11 13:56 ` [PATCH 09/10] drm/i915: Move DPINVGTT setup to vlv_display_irq_reset() ville.syrjala
2016-04-12 11:59 ` Imre Deak
2016-04-11 13:56 ` [PATCH 10/10] Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv" ville.syrjala
2016-04-12 12:04 ` Imre Deak
2016-04-12 17:08 ` Ville Syrjälä
2016-04-12 19:56 ` Chris Wilson
2016-04-11 14:30 ` ✗ Fi.CI.BAT: failure for drm/i915: Fix VLV/CHV unclaimed register errors Patchwork
2016-04-12 16:13 ` Ville Syrjälä
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