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From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
To: Jose Abreu <Jose.Abreu@synopsys.com>
Cc: Carlos Palminha <CARLOS.PALMINHA@synopsys.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	Vineet Gupta <Vineet.Gupta1@synopsys.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-snps-arc@lists.infradead.org"
	<linux-snps-arc@lists.infradead.org>
Subject: Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Date: Thu, 21 Apr 2016 14:15:55 +0000	[thread overview]
Message-ID: <1461248149.2928.26.camel@synopsys.com> (raw)
In-Reply-To: <5718D13B.2040906@synopsys.com>

Hi Jose,

On Thu, 2016-04-21 at 14:10 +0100, Jose Abreu wrote:
> Hi Alexey,
> 
> 
> On 21-04-2016 13:18, Alexey Brodkin wrote:
> > 
> > Hi Jose,
> > 
> > On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote:
> > > 
> > > Hi Alexey,
> > > 
> > Ok reference clock will change.
> > But I may guess we'll still be able to determine at least that new
> > firmware version in run-time, right? If so we'll update a fix-up in
> > early axs10x platform code so that reference clock will be set as 28224000 Hz.
> Yes, there is a register where the FPGA version date is encoded, we can use that
> to check which firmware is used (if date <= old_firmware_date then
> clock=27000000; else clock=28224000). If that fix is acceptable it could be a
> good solution without having to use custom parameters in the DT (no need to
> encode the different clocks and we would only use one master clock) but I am not
> sure where and how this can be encoded and I don't know how to change the DT on
> runtime. Can you give me some guidelines?

Take a look here - http://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/commit/arch/arc/plat-axs10x/axs10x.c?h=for
-next&id=5cd0f5102753a7405548d0c66c11a2a0a05bbf2e

We do something very similar here - we're patching in run-time
core frequency that was specified in .dts.

And in the very same way one will be able to do fix-ups for other
clocks.

Moreover I would propose to think about that fix-up as of completely
separate topic. I.e. in your driver for AXS' I2S clock just use a new
reference "fixed-clock" (that you'll add in "axs10x_mb.dtsi" as a part of
your driver submission). And once your driver gets accepted we'll work on
fix-up in axs10x platform.

This way we'll move with smaller steps and hopefully will get things done
sooner.

> > And indeed 2 DT files is a no go - we want to run the same one binary
> > (with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking about
> > will actually do transformation of .dtb early on kernel boot process so that will
> > be a complete equivalent of different DT files.
> And doing modifications on the DT can cause some misdirections to users.

What do you mean here? What kind of problems do you expect to face?

> Besides, we would have clock specific functions in init procedures which is
> precisely what we are trying to avoid by submitting this driver.

You're talking about fixups above here?

-Alexey

WARNING: multiple messages have this Message-ID (diff)
From: Alexey.Brodkin@synopsys.com (Alexey Brodkin)
To: linux-snps-arc@lists.infradead.org
Subject: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Date: Thu, 21 Apr 2016 14:15:55 +0000	[thread overview]
Message-ID: <1461248149.2928.26.camel@synopsys.com> (raw)
In-Reply-To: <5718D13B.2040906@synopsys.com>

Hi Jose,

On Thu, 2016-04-21@14:10 +0100, Jose Abreu wrote:
> Hi Alexey,
> 
> 
> On 21-04-2016 13:18, Alexey Brodkin wrote:
> > 
> > Hi Jose,
> > 
> > On Thu, 2016-04-21@10:51 +0100, Jose Abreu wrote:
> > > 
> > > Hi Alexey,
> > >?
> > Ok reference clock will change.
> > But I may guess we'll still be able to determine at least that new
> > firmware version in run-time, right? If so we'll update a fix-up in
> > early axs10x platform code so that reference clock will be set as 28224000 Hz.
> Yes, there is a register where the FPGA version date is encoded, we can use that
> to check which firmware is used (if date <= old_firmware_date then
> clock=27000000; else clock=28224000). If that fix is acceptable it could be a
> good solution without having to use custom parameters in the DT (no need to
> encode the different clocks and we would only use one master clock) but I am not
> sure where and how this can be encoded and I don't know how to change the DT on
> runtime. Can you give me some guidelines?

Take a look here -?http://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/commit/arch/arc/plat-axs10x/axs10x.c?h=for
-next&id=5cd0f5102753a7405548d0c66c11a2a0a05bbf2e

We do something very similar here - we're patching in run-time
core frequency that was specified in .dts.

And in the very same way one will be able to do fix-ups for other
clocks.

Moreover I would propose to think about that fix-up as of completely
separate topic. I.e. in your driver for AXS' I2S clock just use a new
reference "fixed-clock" (that you'll add in "axs10x_mb.dtsi" as a part of
your driver submission). And once your driver gets accepted we'll work on
fix-up in axs10x platform.

This way we'll move with smaller steps and hopefully will get things done
sooner.

> > And indeed 2 DT files is a no go - we want to run the same one binary
> > (with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking about
> > will actually do transformation of .dtb early on kernel boot process so that will
> > be a complete equivalent of different DT files.
> And doing modifications on the DT can cause some misdirections to users.

What do you mean here? What kind of problems do you expect to face?

> Besides, we would have clock specific functions in init procedures which is
> precisely what we are trying to avoid by submitting this driver.

You're talking about fixups above here?

-Alexey

  reply	other threads:[~2016-04-21 14:16 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-04 18:00 [PATCH v4] clk/axs10x: Add I2S PLL clock driver Jose Abreu
2016-04-11 10:41 ` [RESEND PATCH " Jose Abreu
2016-04-11 16:47 ` Alexey Brodkin
2016-04-11 16:47   ` Alexey Brodkin
2016-04-11 16:47   ` Alexey Brodkin
2016-04-11 16:47   ` Alexey Brodkin
2016-04-11 22:03   ` sboyd
2016-04-11 22:03     ` sboyd-sgV2jX0FEOL9JmXXK+q4OQ
2016-04-11 22:03     ` sboyd
2016-04-15 12:08     ` Alexey Brodkin
2016-04-15 12:08       ` Alexey Brodkin
2016-04-15 12:08       ` Alexey Brodkin
2016-04-15 23:38       ` sboyd
2016-04-15 23:38         ` sboyd
2016-04-15 23:46 ` Stephen Boyd
2016-04-15 23:46   ` Stephen Boyd
2016-04-18 10:30   ` Jose Abreu
2016-04-18 10:30     ` Jose Abreu
2016-04-18 11:49     ` Vineet Gupta
2016-04-18 11:49       ` Vineet Gupta
2016-04-19  9:13       ` Jose Abreu
2016-04-19  9:13         ` Jose Abreu
2016-04-20  1:54         ` Stephen Boyd
2016-04-20  1:54           ` Stephen Boyd
2016-04-20  9:47           ` Jose Abreu
2016-04-20  9:47             ` Jose Abreu
2016-04-20 16:12             ` Alexey Brodkin
2016-04-20 16:12               ` Alexey Brodkin
2016-04-21  9:51               ` Jose Abreu
2016-04-21  9:51                 ` Jose Abreu
2016-04-21 12:18                 ` Alexey Brodkin
2016-04-21 12:18                   ` Alexey Brodkin
2016-04-21 13:10                   ` Jose Abreu
2016-04-21 13:10                     ` Jose Abreu
2016-04-21 14:15                     ` Alexey Brodkin [this message]
2016-04-21 14:15                       ` Alexey Brodkin
2016-04-22  5:50                   ` Vineet Gupta
2016-04-22  5:50                     ` Vineet Gupta

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