From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 06/10] drm/i915: Bump reserved size for legacy gen8 semaphore emission
Date: Fri, 29 Apr 2016 10:40:41 +0300 [thread overview]
Message-ID: <1461915641.5292.1.camel@linux.intel.com> (raw)
In-Reply-To: <1461860672-12623-6-git-send-email-chris@chris-wilson.co.uk>
On to, 2016-04-28 at 17:24 +0100, Chris Wilson wrote:
> With 5 rings and a flush, we need 192 bytes of space to emit the
> breadcrumb and semaphores. However, we need some spare room the size of
> the single largest packet (36 dwords, 144 bytes) to accommodate
> wraparound giving a grand total of 336 bytes
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Based on the IRC discussion, seems reasonable.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2651fd5263eb..dbf64f8a2356 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -484,10 +484,10 @@ static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
> /*
> * Arbitrary size for largest possible 'add request' sequence. The code paths
> * are complex and variable. Empirical measurement shows that the worst case
> - * is ILK at 136 words. Reserving too much is better than reserving too little
> - * as that allows for corner cases that might have been missed. So the figure
> - * has been rounded up to 160 words.
> + * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
> + * we need to allocate double the largest single packet within that emission
> + * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
> */
> -#define MIN_SPACE_FOR_ADD_REQUEST 160
> +#define MIN_SPACE_FOR_ADD_REQUEST 336
>
> #endif /* _INTEL_RINGBUFFER_H_ */
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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next prev parent reply other threads:[~2016-04-29 7:39 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-28 16:24 [PATCH 01/10] drm/i915: Apply strongly ordered RCS breadcrumb to gen8/legacy Chris Wilson
2016-04-28 16:24 ` [PATCH 02/10] drm/i915: Fix ordering of sanitize ppgtt and sanitize execlists Chris Wilson
2016-04-28 18:48 ` Dave Gordon
2016-04-29 10:59 ` Joonas Lahtinen
2016-04-28 16:24 ` [PATCH 03/10] drm/i915: Fix gen8 semaphores id for legacy mode Chris Wilson
2016-04-29 8:36 ` Tvrtko Ursulin
2016-04-29 8:49 ` Chris Wilson
2016-05-04 11:35 ` Dave Gordon
2016-05-04 11:44 ` Chris Wilson
2016-04-28 16:24 ` [PATCH 04/10] drm/i915: Fix serialisation of pipecontrol write vs semaphore signal Chris Wilson
2016-04-28 16:24 ` [PATCH 05/10] drm/i915: Reload PD tables after semaphore wait on gen8 Chris Wilson
2016-04-28 16:24 ` [PATCH 06/10] drm/i915: Bump reserved size for legacy gen8 semaphore emission Chris Wilson
2016-04-29 7:40 ` Joonas Lahtinen [this message]
2016-04-28 16:24 ` [PATCH 07/10] drm/i915: Trim the flush for the legacy request emission Chris Wilson
2016-04-29 7:43 ` Joonas Lahtinen
2016-04-28 16:24 ` [PATCH 08/10] drm/i915: Trim the flush for the execlists " Chris Wilson
2016-04-29 7:49 ` Joonas Lahtinen
2016-04-28 16:24 ` [PATCH 09/10] drm/i915: Enable semaphores for legacy submission on gen8 Chris Wilson
2016-05-02 8:56 ` Daniel Vetter
2016-04-28 16:24 ` [PATCH 10/10] drm/i915: Enable legacy/semaphores for CI Chris Wilson
2016-04-28 16:56 ` ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915: Apply strongly ordered RCS breadcrumb to gen8/legacy Patchwork
2016-04-29 8:30 ` [PATCH 01/10] " Joonas Lahtinen
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