From: Wei Ni <wni@nvidia.com>
To: edubezval@gmail.com, thierry.reding@gmail.com,
robh+dt@kernel.org, rui.zhang@intel.com
Cc: MLongnecker@nvidia.com, swarren@wwwdotorg.org,
mikko.perttunen@kapsi.fi, linux-tegra@vger.kernel.org,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Wei Ni <wni@nvidia.com>
Subject: [PATCH v3 01/11] of: Add bindings of hw throttle for Tegra soctherm
Date: Tue, 3 May 2016 18:13:20 +0800 [thread overview]
Message-ID: <1462270410-2425-2-git-send-email-wni@nvidia.com> (raw)
In-Reply-To: <1462270410-2425-1-git-send-email-wni@nvidia.com>
Add HW throttle configuration sub-node for soctherm, which
is used to describe the throttle event, and worked as a
cooling device. The "hot" type trip in thermal zone can
be bound to this cooling device, and trigger the throttle
function.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
.../bindings/thermal/nvidia,tegra124-soctherm.txt | 120 ++++++++++++++++++++-
1 file changed, 118 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
index edebfa0a985e..6ba8ae3f59ed 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
@@ -10,8 +10,14 @@ Required properties :
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
For Tegra132, must contain "nvidia,tegra132-soctherm".
For Tegra210, must contain "nvidia,tegra210-soctherm".
-- reg : Should contain 1 entry:
+- reg : Should contain at least 2 entries for each entry in reg-names:
- SOCTHERM register set
+ - Tegra CAR register set: Required for Tegra124 and Tegra210.
+ - CCROC register set: Required for Tegra132.
+- reg-names : Should contain at least 2 entries:
+ - soctherm-reg
+ - car-reg
+ - ccroc-reg
- interrupts : Defines the interrupt used by SOCTHERM
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
@@ -25,17 +31,44 @@ Required properties :
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
list of valid values when referring to thermal sensors.
+- nvidia,throttle-cfgs: A sub-node which is a container of configuration for
+ each hardware throttle events. These events can be set as cooling devices.
+ * throttle events: Sub-nodes must be named as "nvidia,light" or "nvidia,heavy".
+ Properties:
+ - nvidia,priority: Each throttles has its own throttle settings, so the
+ SW need to set priorities for various throttle, the HW arbiter can select
+ the final throttle settings.
+ Bigger value indicates higher priority, In general, higher priority
+ translates to lower target frequency. SW needs to ensure that critical
+ thermal alarms are given higher priority, and ensure that there is
+ no race if priority of two vectors is set to the same value.
+ - nvidia,cpu-throt-depth: This property is for Tegra124 and Tegra210.
+ It is the throttling depth of pulse skippers, it's the percentage
+ throttling.
+ - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
+ level of pulse skippers, which used to throttle clock frequencies. It
+ indicates cpu clock throttling depth, and the depth can be programmed.
+ Must set as following values:
+ TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
+ TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
+ - #cooling-cells: Should be 1. This cooling device only support on/off state.
+ See ./thermal.txt for a description of this property.
Note:
- the "critical" type trip points will be set to SOC_THERM hardware as the
shut down temperature. Once the temperature of this thermal zone is higher
than it, the system will be shutdown or reset by hardware.
+- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
+temperature. Once the the temperature of this thermal zone is higher
+than it, it will trigger the HW throttle event.
Example :
soctherm@700e2000 {
compatible = "nvidia,tegra124-soctherm";
- reg = <0x0 0x700e2000 0x0 0x1000>;
+ reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
+ 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
+ reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
@@ -44,6 +77,76 @@ Example :
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
+
+ nvidia,throttle-cfgs {
+ /*
+ * When the "heavy" cooling device triggered,
+ * the HW will skip cpu clock's pulse in 85% depth
+ */
+ throttle_heavy: nvidia,heavy {
+ nvidia,priority = <100>;
+ nvidia,cpu-throt-depth = <85>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * When the "light" cooling device triggered,
+ * the HW will skip cpu clock's pulse in 50% depth
+ */
+ throttle_light: nvidia,light {
+ nvidia,priority = <80>;
+ nvidia,cpu-throt-depth = <50>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * If these two devices are triggered in same time, the HW throttle
+ * arbiter will select the highest priority as the final throttle
+ * settings to skip cpu pulse.
+ */
+ };
+ };
+
+Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
+
+ soctherm@0,700e2000 {
+ compatible = "nvidia,tegra132-soctherm";
+ reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
+ 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
+ reg-names = "soctherm-reg", "ccroc-reg";
+
+ nvidia,throttle-cfgs {
+ /*
+ * When the "heavy" cooling device triggered,
+ * the HW will skip cpu clock's pulse in HIGH level
+ */
+ throttle_heavy: nvidia,heavy {
+ nvidia,priority = <100>;
+ nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * When the "light" cooling device triggered,
+ * the HW will skip cpu clock's pulse in MED level
+ */
+ throttle_light: nvidia,light {
+ nvidia,priority = <80>;
+ nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * If these two devices are triggered in same time, the HW throttle
+ * arbiter will select the highest priority as the final throttle
+ * settings to skip cpu pulse.
+ */
+
+ };
};
Example: referring to thermal sensors :
@@ -62,6 +165,19 @@ Example: referring to thermal sensors :
hysteresis = <1000>;
type = "critical";
};
+
+ cpu_throttle_trip: throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_throttle_trip>;
+ cooling-device = <&throttle_heavy 1 1>;
+ };
};
};
};
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Wei Ni <wni@nvidia.com>
To: <edubezval@gmail.com>, <thierry.reding@gmail.com>,
<robh+dt@kernel.org>, <rui.zhang@intel.com>
Cc: <MLongnecker@nvidia.com>, <swarren@wwwdotorg.org>,
<mikko.perttunen@kapsi.fi>, <linux-tegra@vger.kernel.org>,
<linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Wei Ni <wni@nvidia.com>
Subject: [PATCH v3 01/11] of: Add bindings of hw throttle for Tegra soctherm
Date: Tue, 3 May 2016 18:13:20 +0800 [thread overview]
Message-ID: <1462270410-2425-2-git-send-email-wni@nvidia.com> (raw)
In-Reply-To: <1462270410-2425-1-git-send-email-wni@nvidia.com>
Add HW throttle configuration sub-node for soctherm, which
is used to describe the throttle event, and worked as a
cooling device. The "hot" type trip in thermal zone can
be bound to this cooling device, and trigger the throttle
function.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
.../bindings/thermal/nvidia,tegra124-soctherm.txt | 120 ++++++++++++++++++++-
1 file changed, 118 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
index edebfa0a985e..6ba8ae3f59ed 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
@@ -10,8 +10,14 @@ Required properties :
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
For Tegra132, must contain "nvidia,tegra132-soctherm".
For Tegra210, must contain "nvidia,tegra210-soctherm".
-- reg : Should contain 1 entry:
+- reg : Should contain at least 2 entries for each entry in reg-names:
- SOCTHERM register set
+ - Tegra CAR register set: Required for Tegra124 and Tegra210.
+ - CCROC register set: Required for Tegra132.
+- reg-names : Should contain at least 2 entries:
+ - soctherm-reg
+ - car-reg
+ - ccroc-reg
- interrupts : Defines the interrupt used by SOCTHERM
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
@@ -25,17 +31,44 @@ Required properties :
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
list of valid values when referring to thermal sensors.
+- nvidia,throttle-cfgs: A sub-node which is a container of configuration for
+ each hardware throttle events. These events can be set as cooling devices.
+ * throttle events: Sub-nodes must be named as "nvidia,light" or "nvidia,heavy".
+ Properties:
+ - nvidia,priority: Each throttles has its own throttle settings, so the
+ SW need to set priorities for various throttle, the HW arbiter can select
+ the final throttle settings.
+ Bigger value indicates higher priority, In general, higher priority
+ translates to lower target frequency. SW needs to ensure that critical
+ thermal alarms are given higher priority, and ensure that there is
+ no race if priority of two vectors is set to the same value.
+ - nvidia,cpu-throt-depth: This property is for Tegra124 and Tegra210.
+ It is the throttling depth of pulse skippers, it's the percentage
+ throttling.
+ - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
+ level of pulse skippers, which used to throttle clock frequencies. It
+ indicates cpu clock throttling depth, and the depth can be programmed.
+ Must set as following values:
+ TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
+ TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
+ - #cooling-cells: Should be 1. This cooling device only support on/off state.
+ See ./thermal.txt for a description of this property.
Note:
- the "critical" type trip points will be set to SOC_THERM hardware as the
shut down temperature. Once the temperature of this thermal zone is higher
than it, the system will be shutdown or reset by hardware.
+- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
+temperature. Once the the temperature of this thermal zone is higher
+than it, it will trigger the HW throttle event.
Example :
soctherm@700e2000 {
compatible = "nvidia,tegra124-soctherm";
- reg = <0x0 0x700e2000 0x0 0x1000>;
+ reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
+ 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
+ reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
@@ -44,6 +77,76 @@ Example :
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
+
+ nvidia,throttle-cfgs {
+ /*
+ * When the "heavy" cooling device triggered,
+ * the HW will skip cpu clock's pulse in 85% depth
+ */
+ throttle_heavy: nvidia,heavy {
+ nvidia,priority = <100>;
+ nvidia,cpu-throt-depth = <85>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * When the "light" cooling device triggered,
+ * the HW will skip cpu clock's pulse in 50% depth
+ */
+ throttle_light: nvidia,light {
+ nvidia,priority = <80>;
+ nvidia,cpu-throt-depth = <50>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * If these two devices are triggered in same time, the HW throttle
+ * arbiter will select the highest priority as the final throttle
+ * settings to skip cpu pulse.
+ */
+ };
+ };
+
+Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
+
+ soctherm@0,700e2000 {
+ compatible = "nvidia,tegra132-soctherm";
+ reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
+ 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
+ reg-names = "soctherm-reg", "ccroc-reg";
+
+ nvidia,throttle-cfgs {
+ /*
+ * When the "heavy" cooling device triggered,
+ * the HW will skip cpu clock's pulse in HIGH level
+ */
+ throttle_heavy: nvidia,heavy {
+ nvidia,priority = <100>;
+ nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * When the "light" cooling device triggered,
+ * the HW will skip cpu clock's pulse in MED level
+ */
+ throttle_light: nvidia,light {
+ nvidia,priority = <80>;
+ nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+
+ #cooling-cells = <1>;
+ };
+
+ /*
+ * If these two devices are triggered in same time, the HW throttle
+ * arbiter will select the highest priority as the final throttle
+ * settings to skip cpu pulse.
+ */
+
+ };
};
Example: referring to thermal sensors :
@@ -62,6 +165,19 @@ Example: referring to thermal sensors :
hysteresis = <1000>;
type = "critical";
};
+
+ cpu_throttle_trip: throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_throttle_trip>;
+ cooling-device = <&throttle_heavy 1 1>;
+ };
};
};
};
--
1.9.1
next prev parent reply other threads:[~2016-05-03 10:13 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-03 10:13 [PATCH v3 00/11] Add HW throttle for Tegra soctherm Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` Wei Ni [this message]
2016-05-03 10:13 ` [PATCH v3 01/11] of: Add bindings of hw " Wei Ni
[not found] ` <1462270410-2425-2-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-05-04 13:35 ` Rob Herring
2016-05-04 13:35 ` Rob Herring
2016-05-05 3:29 ` Wei Ni
2016-05-05 3:29 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 02/11] thermal: tegra: add hw-throttle function Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 03/11] thermal: tegra: add hw-throttle for Tegra132 Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 04/11] arm: tegra: set critical trips for Tegra124 Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 05/11] arm: tegra: set hot " Wei Ni
2016-05-03 10:13 ` Wei Ni
[not found] ` <1462270410-2425-1-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-05-03 10:13 ` [PATCH v3 06/11] arm64: tegra: use tegra132-soctherm for Tegra132 Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 07/11] arm64: tegra: set critical trips " Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 08/11] arm64: tegra: set hot " Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 09/11] arm64: tegra: add soctherm node for Tegra210 Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 10/11] arm64: tegra: set critical trips " Wei Ni
2016-05-03 10:13 ` Wei Ni
2016-05-03 10:13 ` [PATCH v3 11/11] arm64: tegra: set hot " Wei Ni
2016-05-03 10:13 ` Wei Ni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1462270410-2425-2-git-send-email-wni@nvidia.com \
--to=wni@nvidia.com \
--cc=MLongnecker@nvidia.com \
--cc=devicetree@vger.kernel.org \
--cc=edubezval@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mikko.perttunen@kapsi.fi \
--cc=robh+dt@kernel.org \
--cc=rui.zhang@intel.com \
--cc=swarren@wwwdotorg.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.