[PATCH 0/7] x86/ras: RAS queue

[Borislav Petkov <bp@alien8.de>]

From: Borislav Petkov <bp@suse.de>

Hi,

here's the last pile that got ready. It is mostly SMCA enablement for
future AMD F17h CPUs so the remaining families shouldn't be affected.
Initial testing on what I have here looks ok, randconfigs pass too.

All is ontop of tip:ras/core.

Thanks.

Borislav Petkov (1):
  x86/mce/AMD: Save an indentation level in prepare_threshold_block()

Yazen Ghannam (6):
  x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR}
    registers
  x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems
  x86/cpu: Add detection of AMD RAS Capabilities
  x86/mce: Update AMD mcheck init to use cpu_has() facilities
  EDAC, mce_amd: Detect SMCA using X86_FEATURE_SMCA
  x86/RAS: Add SMCA support to AMD Error Injector

 arch/x86/include/asm/cpufeature.h    |  1 +
 arch/x86/include/asm/cpufeatures.h   |  7 ++-
 arch/x86/include/asm/mce.h           |  4 ++
 arch/x86/kernel/cpu/common.c         | 10 ++--
 arch/x86/kernel/cpu/mcheck/mce.c     |  8 ++--
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 92 ++++++++++++++++++++++++------------
 arch/x86/ras/mce_amd_inj.c           | 31 +++++++++---
 drivers/edac/mce_amd.c               |  9 ++--
 8 files changed, 112 insertions(+), 50 deletions(-)

-- 
2.7.3